AMD EPYC 9355 socket: SP5

What the EPYC 9355 is

The EPYC 9355 is a 32-core, 64-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.55 GHz base with boost to 4.4 GHz and all-core boost at 4.2 GHz. Shared L3 cache totals 256 MB. Default TDP is 280 W configurable between 240 and 300 W.

Large cache with high clocks defines this SKU for database duty: 8 MB of L3 per core backs per-core licensed databases that stay resident in cache, while 3.55 GHz base keeps sustained throughput strong for virtualization beside them. Against the 32-core AMD EPYC 9335 at 210 W it spends power for 550 MHz more base clock with double the cache for demanding tenants. The single-socket twin AMD EPYC 9355P is the 1P twin on cheaper boards for edge database duty.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The combination suits virtualization hosts where a few fast, cache-rich cores outperform many slower ones per guest in production.

Workload fit centers on databases and VDI around the clock: buffer pools that fit in 256 MB fly, while guests with steady CPU demand benefit from the high base across long shifts and maintenance windows. Operators often dedicate 9355 hosts to licensed tiers and run unlicensed scale-out guests on denser, cheaper-per-thread SKUs beside them in the same racks every refresh cycle without relicensing churn.

Socket and motherboard compatibility

The 9355 fits the SP5 socket as an FC-LGA6096 part on 280 W-class server boards built for database duty. Genoa boards accept Turin after a firmware update with the new stepping for production database fleets. The board maker CPU support list confirms the SKU with its minimum BIOS, and delivery covers the upper configurable bound for sustained database throughput.

One or two sockets are supported. Mid-size core counts with big caches suit buyers who license per core for predictable database budgets: two sockets give 64 fast cores with full 24-channel memory for database clusters. Socket-count licensing treats the pair like any other Turin combination for straightforward renewals.

Genoa-era boards generally accept Turin after a firmware update with validated stepping support for production fleets. Mixed fleets of cache-rich and dense SKUs share firmware trains and spares across both for simpler operations at any scale.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Large cache reduces memory pressure, but fully populated channels still matter for bandwidth uniformity across 32 cores under full load. The board memory guide sets legal mixes for the 280 W class and warm data halls running year-round.

PCIe 5.0 x128 lanes per socket with CXL 2.0 attach NVMe, networking and accelerators. Slot widths follow the board design with exact splits in the manual for each chassis variant. Database hosts should wire redo logs to low-latency NVMe on CPU-attached slots for consistent commit times.

Cooling at 280 W uses vendor-qualified air or liquid heatsinks matched to chassis height and duty cycle. No tray cooler ships. Standard 2U air cooling usually covers this class, while compact designs need the vendor high-performance option validated for the enclosure.

Upgrade paths

Within SP5 the 9355 grows from the 32-core AMD EPYC 9335 for clocks and cache at higher power, or trims from larger SKUs for cost. The single-socket AMD EPYC 9355P is the 1P twin on cheaper boards. Each move needs only a BIOS check with matching cooling and airflow validation for the new envelope.

Frequency-optimized F SKUs such as the AMD EPYC 9275F serve higher clocks on the same boards for latency-critical database tiers. A full platform exit waits for post-SP5 sockets with fresh memory qualification for future clusters.