AMD EPYC 9135 socket: SP5
The AMD EPYC 9135 uses the SP5 socket. It is a 16-core Turin server processor at 200 W with high base clocks for infrastructure and virtualization hosts.
AMD EPYC 9135 specifications
| Cores | 16 |
|---|---|
| Threads | 32 |
| Core architecture | Zen 5 |
| Clocks | 3.65 GHz base to 4.3 GHz boost |
| Cache | 64 MB L3 |
| Default TDP | 200 W |
| Manufacturing process | TSMC 4 nm for the compute dies, 6 nm for the I/O die |
| Memory support | DDR5 up to 6400 MT/s, ECC RDIMM, 12 channels, up to 6 TB per socket |
| PCI Express | PCIe 5.0 x128 per socket, with CXL 2.0 |
| ECC memory | ECC through DDR5 RDIMM |
| Package | SP5 (LGA6096) |
| Sockets supported | 1P and 2P |
Motherboard compatibility
AMD EPYC 9135 needs a motherboard with a SP5 socket. Chipset by chipset data for this codename is not recorded yet. See the SP5 chipset list and the board maker's CPU support list.
SP5 at a glance
| Type | LGA, 6,096 contacts |
|---|---|
| Package size | 72 × 75.4 mm |
| Introduced | November 2022 |
| Memory | DDR5 ECC RDIMM, 12 channels (up to DDR5-6000, DDR5-6400 in target configs, up to 6 TB per socket) |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 9135 is
The EPYC 9135 is a 16-core, 32-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.65 GHz base with boost to 4.3 GHz and all-core boost at 4.25 GHz. Shared L3 cache totals 64 MB across two compute dies. Default TDP is 200 W configurable between 200 and 240 W.
A note on sources: a partner page printed 128 MB of cache for this SKU, but the AMD product page and datasheet agree on 64 MB, which this page follows. High 3.65 GHz base clocks with full platform I/O define the value: infrastructure guests stay responsive while HBAs and NICs use all 128 lanes. The embedded twin AMD EPYC Embedded 9135 serves industrial carriers with long availability windows.
There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Against the 16-core AMD EPYC 9115 at 125 W the 9135 spends power for a full gigahertz more base clock, which shows in sustained virtualization throughput.
Workload fit is responsive infrastructure: virtual desktop brokers, CI runners and network services where base clocks decide user experience. Operators pick the 9135 for hosts that stay busy all day, since sustained speed there outweighs idle efficiency and the 200 W envelope still fits standard racks with room to spare.
Platform consistency is the quiet advantage: the 9135 shares socket, memory generation and management tooling with every other Turin SKU, so operators deploy it beside dense hosts without new training or spares. Mixed fleets cover infrastructure and guests from one firmware train, which simplifies lifecycle management across all sites.
Socket and motherboard compatibility
The 9135 fits the SP5 socket in FC-LGA6096 packaging on 200 W-class server boards. Genoa boards accept it with Turin-capable firmware. The board maker CPU support list confirms the SKU with its minimum BIOS, and delivery covers the upper configurable bound.
One or two sockets are supported, with single-socket infrastructure builds the common case. Full 12-channel memory and 128 lanes stay available, so storage and network features never step down with core count for infrastructure duty. Hyperconverged nodes pair the 9135 with local NVMe for branch duty and fast recovery.
Fleets standardizing on SP5 mix the 9135 with denser Turin SKUs under shared firmware for unified operations. Remote sites benefit from moderate thermals that fit small racks without special cooling or airflow engineering.
Memory, PCIe and cooling
DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Infrastructure hosts rarely fill the ceiling, but channels exist for hyperconverged caches that grow with data. Even population keeps bandwidth uniform across both CCDs. Backup nodes should size memory for deduplication tables first before adding disk shelves.
PCIe 5.0 x128 lanes with CXL 2.0 give HBAs, NICs and NVMe the full Turin budget. Few entry boards wire every lane, yet controllers never wait on this CPU for demanding infrastructure duty. Board manuals define the fitted slots for each chassis and workload.
Cooling at 200 W uses standard air heatsinks. No tray cooler ships. This class cools easily in most chassis, which suits branch closets and warm sites. Operators should still confirm sustained boost under local ambients before signing off on branch deployments.
Upgrade paths
Within SP5 the 9135 grows from the 16-core AMD EPYC 9115 for base clocks at higher power, or steps to the 24-core AMD EPYC 9255 for threads. Boards and memory carry over with a BIOS check. Power feeds deserve a recheck before any jump past 155 W into higher server classes with stronger delivery.
Because the socket and I/O stay constant, upgrades need only power and cooling headroom for reliable operation across sites. Platform exits wait for later sockets with better efficiency characteristics.
Frequently asked questions
What socket does the EPYC 9135 use?
It uses SP5 in the FC-LGA6096 package on 200 W-class server boards.
How much cache does the EPYC 9135 have?
64 MB of shared L3 cache. A partner page printed 128 MB, but the AMD product page and datasheet confirm 64 MB.
What are the clocks of the EPYC 9135?
3.65 GHz base with boost to 4.3 GHz, a high base clock for infrastructure duty.
What is the TDP of the EPYC 9135?
200 W default, configurable between 200 and 240 W.
What memory does the EPYC 9135 support?
DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs, to 6 TB per socket.
Sources and verification
Facts last checked against these sources on . Page last edited on .