AMD EPYC 9355P socket: SP5

What the EPYC 9355P is

The EPYC 9355P is a 32-core, 64-thread server processor that AMD released on October 10, 2024 for single-socket Turin systems. Zen 5 cores run at 3.55 GHz base with boost to 4.4 GHz and all-core boost at 4.2 GHz. Shared L3 cache totals 256 MB. Default TDP is 280 W configurable between 240 and 300 W.

High base clocks with a large cache define this SKU: 3.55 GHz base is the fastest sustained clock among the 32-core Turin options, and 256 MB of L3 gives 8 MB per core for cache-hungry guests running daily production loads. The P suffix marks 1P boards, while the AMD EPYC 9355 matches the silicon for dual-socket layouts with room to grow. The embedded twin AMD EPYC Embedded 9355P serves industrial carriers.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Edge virtualization and high-performance branch hosts value the combination of speed and single-socket simplicity every day. Configurable TDP down to 240 W fits power-capped sites without changing SKUs or recertifying boards.

Workload fit centers on per-core licensing: databases and VDI brokers that charge per core run cheapest where fewer, faster cores carry the load, which is exactly the 9355P recipe. Operators often reserve the 9355P for licensed tiers while dense SKUs such as the AMD EPYC 9555 handle unlicensed scale-out guests beside them.

Socket and motherboard compatibility

The 9355P fits the SP5 socket in FC-LGA6096 packaging on single-socket server boards with 280 W delivery. Only 1P designs qualify despite the shared socket. The board maker CPU support list confirms the SKU with its minimum BIOS, and power stages cover the upper configurable bound.

Choosing P over non-P is a purchase-time platform call: 1P boards cost less with flat NUMA, while 2P boards with the AMD EPYC 9355 keep a second socket open. Memory bandwidth per core matches at 12 channels either way for identical guest performance. Operators with per-core licensed stacks often prefer the P shape because socket counts stay fixed for audits and renewals.

Genoa-era boards accept Turin after a firmware update with validated stepping support for production fleets. Confirm per board revision rather than assuming socket compatibility alone. Mixed fleets share firmware and spares across P and non-P hosts.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB in one socket. Generous cache plus wide channels suit per-core licensed databases that stay on one socket by design. Fully populated channels with matched DIMMs keep bandwidth uniform. The board memory guide sets legal mixes for the 280 W class. Database sizing should start from buffer-pool targets, since cache hit rates decide transaction throughput more than core counts do.

PCIe 5.0 x128 lanes with CXL 2.0 serve NVMe, networking and accelerators from the single CPU. Slot bifurcation follows the 1P board layout for straightforward device trees. Uniform latency without inter-socket hops helps latency-sensitive branch applications meet service targets.

Cooling at 280 W uses vendor-qualified air or liquid heatsinks matched to chassis height and duty cycle. No tray cooler ships with this single-socket performance class. Single-socket 2U bodies cool this class comfortably, while compact 1U designs need the vendor high-performance option selected for the enclosure.

Upgrade paths

Inside single-socket SP5 the 9355P grows from smaller P SKUs for threads or steps to the 48-core AMD EPYC 9455P for density, reusing board and memory with a BIOS check. Power steps follow the SKU envelope with matching cooling and airflow validation. Operators should revalidate capping policies after any move between power classes.

Moving to dual-socket means new boards with the AMD EPYC 9355 instead for socket expansion room. Leaving SP5 entirely waits for later sockets with fresh memory qualification across the fleet.