AMD EPYC 9365 socket: SP5

What the EPYC 9365 is

The EPYC 9365 is a 36-core, 72-thread server processor that AMD released on October 10, 2024 in the EPYC 9005 series. Zen 5 Turin cores run at 3.4 GHz base with boost to 4.3 GHz and all-core boost at 4.15 GHz. Shared L3 cache totals 192 MB across six compute dies. Default TDP is 300 W configurable between 240 and 300 W.

A note on sources: an early datasheet excerpt printed 4.2 GHz boost with 128 MB of cache for this SKU, but the AMD product page and the database agree on 4.3 GHz with 192 MB, which this page follows. Against the 32-core AMD EPYC 9335 the 9365 adds four cores with higher base clocks for hosts that sell steady throughput. Against the 48-core AMD EPYC 9455 it trades cores for cost per socket. Six CCDs keep the die layout balanced for NUMA placement.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs provide correction. Two threads per core give 72 threads per socket for guest placement. Configurable TDP down to 240 W lets operators fit existing power budgets without changing SKUs.

Socket and motherboard compatibility

The 9365 fits the SP5 socket as an FC-LGA6096 part on boards qualified for the 300 W class. Genoa-era boards generally accept Turin after a firmware update carrying the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS. Power delivery and retention hardware on qualified boards assume the full 300 W envelope with margin.

One or two sockets per system are supported. Mid-range core counts like this one suit buyers who license per core or who balance sockets against memory capacity: two 9365 sockets give 72 cores with full 24-channel memory for database clusters. Socket-count licensing often decides between one dense socket and two balanced ones.

Single-socket buyers with the same budget compare the P-series for 1P boards. The socket, memory generation and PCIe generation stay identical across that choice. Mixed fleets of 9365 and 9335 hosts share firmware trains and management tooling.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s across 12 channels with ECC RDIMMs reaches 6 TB per socket. At 36 cores the bandwidth per core is generous, which suits memory-hungry analytics beside virtualization. Populate all channels evenly and follow the board guide for 6400-capable DIMM selections. Hosts that consolidate databases per socket should size memory before cores, since working sets decide performance here.

PCIe 5.0 x128 lanes with CXL 2.0 attach NVMe, networking and accelerators directly to the CPU. Slot widths follow the board design, with exact bifurcation in the manual. CXL memory expanders fit hosts that need capacity beyond DIMM limits. Network-heavy builds should confirm NIC placement on CPU-attached slots for the lowest latency.

Cooling at 300 W uses vendor-qualified air or liquid heatsinks per chassis. No tray cooler ships. Standard 2U air cooling usually covers this class, while 1U bodies need the vendor high-performance sink. Operators should validate sustained all-core clocks under their own load mix before signing off.

Upgrade paths

Within SP5 the 9365 steps up from the 32-core AMD EPYC 9335 for core count or down in power for efficiency, keeping boards and memory. The 48-core AMD EPYC 9455 above adds threads for denser guests at the same 300 W. Each move needs only a BIOS check with matching cooling. Operators should revalidate power capping policies after any swap, since cTDP ranges differ by SKU.

Frequency-optimized F SKUs such as the AMD EPYC 9175F serve licensed per-core speed on the same boards. A full platform exit waits for post-SP5 sockets. Refresh cycles normally align with warranty terms, so the socket choice outlives any single deployment.