AMD EPYC Embedded 9535 socket: SP5

What the AMD EPYC Embedded 9535 is

The AMD EPYC Embedded 9535 is the 64-core efficiency-tuned member of the EPYC Embedded 9005 Turin stack on Socket SP5. It runs 128 threads at 2.4 GHz base with boost to 4.3 GHz, backed by 256 MB of L3 cache and a 300 W default TDP. AMD announced the Embedded 9005 series on March 11, 2025 with production shipments expected in the second quarter of 2025, building the Zen 5 chiplets on a 4 nm process with a 6 nm I/O die.

Sixty-four cores at a modest base clock suit consolidation hosts, private cloud nodes, video and analytics pipelines where throughput per watt matters more than peak frequency. Lower base clocks keep the 300 W envelope in reach for standard air-cooled racks, while boost still lifts bursty threads to 4.3 GHz. The 256 MB L3 pool spreads across the CCDs to keep data near the cores.

Against the 48-core AMD EPYC Embedded 9455P beside it, the 9535 adds 16 cores for denser virtual machines at the same 300 W class. Against the higher-clock 64-core AMD EPYC Embedded 9555 above it, the 9535 trades base frequency for lower power draw. Long-life firmware and 7-year manufacturing support suit carrier and industrial builds. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Socket and motherboard compatibility

The 9535 fits Socket SP5, a 6,096-contact land grid array that AMD built for EPYC 9004 Genoa and EPYC 9005 Turin processors. Boards support one or two sockets with this non-P part, so one 9535 fills a balanced appliance or pairs with an identical 9535 in a dual-socket node. SP5 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor.

Turin shares SP5 packaging with Genoa, so many Genoa boards take the 9535 after a BIOS update from the board maker at the same power class. A 9535 at 300 W fits boards already rated for 300 W Genoa parts, which keeps thermals and power delivery inside known limits. Memory on an older board may stay at the Genoa qualified speed rather than reaching DDR5-6000, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP5 socket feeds 12 DDR5 channels with ECC RDIMM or 3DS RDIMM modules, and AMD rates Turin to 6000 MT/s with 6400 MT/s in target configs for up to 6 TB per socket. Twelve channels keep 128 threads supplied in virtualization, analytics and storage mixes. Population order and maximum capacity vary by board, so the vendor memory list governs every build, and dual-socket builds use matched DIMM populations.

PCI Express connectivity is Gen 5 with x128 lanes per socket, plus x8 Gen 3 lanes for board devices and slower slots. That lane budget feeds NVMe arrays, high-speed networking and accelerators without lane sharing pressure. CXL 2.0 memory expansion is part of the Turin platform where the board wires it, and bifurcation follows board firmware, so architects confirm slot maps before committing to a dense layout.

Cooling follows the board vendor list rather than a retail box. SP5 uses server retention with heatsinks validated per TDP class, and the 9535 at 300 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a site demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9535 starts with the 64-core AMD EPYC Embedded 9555 for higher clocks and the 96-core AMD EPYC Embedded 9655 for more cores, all staying on SP5 boards where power and cooling allow. The dense-core AMD EPYC Embedded 9745 follows for throughput-first racks. Each move keeps board and memory investments where the TDP class allows, plus a BIOS that already supports Turin.

The step down to the 48-core AMD EPYC Embedded 9455P trims core count while keeping the 300 W class for license-sensitive sites. A move to AM5 entry servers is a different platform with 2 memory channels and far lower power classes. That change replaces board, memory population and cooling design from scratch. The decision turns on cores per watt against per-core speed.