AMD EPYC 9255 socket: SP5

What the EPYC 9255 is

The EPYC 9255 is a 24-core, 48-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.2 GHz base with boost to 4.3 GHz and all-core boost at 4.0 GHz. Shared L3 cache totals 128 MB. Default TDP is 200 W configurable between 200 and 240 W.

A note on sources: the CPU list gives 3.25 GHz base with 4.8 GHz boost, but the AMD product page and datasheet agree on 3.2 GHz base with 4.3 GHz boost. The 4.8 GHz figure belongs to the frequency-optimized AMD EPYC 9275F, so this page follows AMD. Against the 32-core AMD EPYC 9335 nearby it trades threads for lower power at similar clocks.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 200 W envelope fits power-capped racks and edge sites where 300 W SKUs cannot go for thermal reasons or policy limits. High 3.2 GHz base clocks keep interactive guests responsive during working hours and batch windows alike.

Workload fit is efficient virtualization: hyperconverged nodes, backup infrastructure and management clusters where 24 cores cover the guests and watts stay capped. Operators often choose the 9255 where the alternative was denser silicon running half-idle, since right-sized hosts waste less power and fewer licenses across the entire estate.

Platform consistency is the quiet advantage: the 9255 shares socket, memory generation and management tooling with every other Turin SKU, so operators deploy it beside dense hosts without new training or spares. Mixed fleets of efficient and dense nodes cover branch and core sites from one firmware train, which simplifies lifecycle management across the estate.

Socket and motherboard compatibility

The 9255 fits the SP5 socket as an FC-LGA6096 part on 200 W-class server boards. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and delivery covers the upper configurable bound.

One or two sockets are supported. Efficient 24-core hosts suit branch virtualization and hyperconverged nodes where power feeds cap bigger chips. Dual-socket pairs stay near 400 W for both processors with 48 cores total. Operators with strict per-rack power limits fit more 9255 hosts per row than with 300 W silicon.

Fleets mix the 9255 with denser Turin SKUs under shared firmware and management for simpler operations. The socket, memory generation and PCIe generation stay constant across the mix for common spares.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Per-core bandwidth at 24 cores is generous, which flatters memory-bound guests on efficient hosts. Even channel population keeps performance uniform for branch clusters large and small. Hyperconverged nodes should size memory for cache tiers first before adding disk groups.

PCIe 5.0 x128 lanes with CXL 2.0 serve NVMe, networking and accelerators. Few efficient boards wire every lane, yet controllers never wait on this CPU. Board manuals define the fitted slots per chassis for each deployment profile and power budget.

Cooling at 200 W uses standard air heatsinks in most chassis. No tray cooler ships. This is among the easiest Turin classes to cool, which suits remote sites with simple maintenance and warm ambients.

Upgrade paths

Within SP5 the 9255 grows from smaller efficient SKUs or steps to the 32-core AMD EPYC 9335 for threads, reusing boards and memory with a BIOS check. The frequency-optimized AMD EPYC 9275F above trades power for clocks at the same core count. Each move needs matching cooling for the higher envelope.

Platform exits wait for later sockets with fresh memory qualification for future branch refreshes. Efficient hosts often serve a full second life at the edge after datacenter duty, which favors starting on a long-lived socket platform.