AMD EPYC 9115 socket: SP5

What the EPYC 9115 is

The EPYC 9115 is a 16-core, 32-thread server processor that AMD released on October 10, 2024 with the Turin family. Zen 5 cores run at 2.6 GHz base with boost to 4.1 GHz and all-core boost at 3.3 GHz. Shared L3 cache totals 64 MB across two compute dies. Default TDP is 125 W configurable between 120 and 155 W.

It doubles the threads of the 8-core AMD EPYC 9015 at the same 125 W, which makes it the sweet spot for infrastructure virtualization on a budget. Management clusters, backup servers and branch hosts run their guests here while dense SKUs such as the AMD EPYC 9555 handle the main datacenter floor. Two CCDs keep latency uniform across all cores. Operators often pin infrastructure VMs to the 9115 hosts and keep business workloads on denser silicon, which simplifies capacity planning across tiers.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 2.6 GHz base sips power at idle while 4.1 GHz boost answers interactive logins without delay. Configurable TDP up to 155 W covers warm sites where sustained boost matters. Baseboard controllers monitor per-socket power so racks stay inside provisioned feeds.

Socket and motherboard compatibility

The 9115 fits the SP5 socket in FC-LGA6096 packaging on low-power server boards. Genoa boards accept it with Turin-capable firmware carrying the new stepping. The board maker CPU support list confirms the SKU with the minimum BIOS, and power delivery on qualified boards covers the 155 W upper bound.

One or two sockets are supported, with single-socket builds the common case for this class. Full 12-channel memory and 128 PCIe lanes stay available, so infrastructure features never step down with core count. Hyperconverged nodes often pair the 9115 with local NVMe for branch offices. Dual-socket 9115 pairs suit sites that want thread headroom without leaving the efficient power band.

Fleets standardizing on SP5 mix the 9115 with bigger Turin SKUs under shared firmware and management. Remote sites benefit from the modest thermal output, which fits small racks and telco cabinets without special cooling. Spare DIMMs and heatsinks interchange across the fleet since the platform stays constant.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Infrastructure hosts rarely fill that ceiling, but the channels exist for hyperconverged caches that grow with data. Even population keeps bandwidth uniform across the two CCDs. Backup servers should size memory for deduplication tables first, since hit rates decide throughput. Storage-heavy nodes benefit from read-mostly cache sizing before adding spindles.

PCIe 5.0 x128 lanes with CXL 2.0 give HBAs, NICs and NVMe the full Turin I/O budget. Few entry boards wire every lane, yet network and storage controllers never wait on this CPU. Board manuals define the fitted slots for each chassis. A pair of 100-gigabit NICs plus boot NVMe covers most infrastructure builds with lanes to spare.

Cooling at 125 W uses standard air heatsinks. No tray cooler ships. This class fits quiet racks and branch closets without special handling. Operators should still confirm sustained boost under local ambient conditions before signing off.

Upgrade paths

Within SP5 the 9115 grows from the 8-core AMD EPYC 9015 for threads at the same power, or steps to the 32-core AMD EPYC 9335 for guests with higher draw. Boards and memory carry over with a BIOS check. Power feeds deserve a recheck before any jump past 155 W.

Because the socket and I/O stay constant, upgrades need only power and cooling headroom for reliable daily operation. Platform exits wait for later sockets with better efficiency characteristics. Infrastructure hosts often serve full depreciation cycles before any socket change, which favors starting on a long-lived platform.