AMD EPYC 9455 socket: SP5

What the EPYC 9455 is

The EPYC 9455 is a 48-core, 96-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.15 GHz base with boost to 4.4 GHz and all-core boost at 4.1 GHz. Shared L3 cache totals 256 MB across eight compute dies of about 70.6 sq mm each. Default TDP is 300 W configurable between 240 and 300 W.

A note on sources: launch tables in the press release and one review printed 192 MB of cache for this SKU, but the AMD product page confirms 256 MB, which this page follows as the authoritative per-SKU figure. Against the 64-core AMD EPYC 9555 the 9455 trades threads for cost per socket with high base clocks intact. Against the 36-core AMD EPYC 9365 it adds 12 cores for denser guests. Eight CCDs balance cache and cores evenly for mixed virtualization duty.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs provide correction. The 3.15 GHz base keeps sustained throughput high for virtualization hosts that rarely boost across all cores at once. Mid-size clouds often standardize on 48-core hosts because the guest-to-host ratio stays manageable for operations teams.

Socket and motherboard compatibility

The 9455 fits the SP5 socket as an FC-LGA6096 part on 300 W-class server boards with validated power delivery. Genoa boards accept Turin after a firmware update with the new stepping confirmed for mainstream virtualization clusters. The board maker CPU support list confirms the SKU with its minimum BIOS, and power delivery assumes the upper configurable bound.

One or two sockets are supported. The 48-core size suits mainstream virtualization clusters: two sockets give 96 cores with 24 memory channels for balanced guests, while single-socket builds serve branch hosts. Socket-count licensing often favors this middle size over denser options. Operators like the even split because failover math stays simple when one host covers another.

Single-socket buyers compare P-series SKUs for 1P boards at similar budgets with lower platform costs. The socket, memory generation and PCIe generation stay identical, so density per dollar decides.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 48 cores the capacity per core supports memory-sized guests beside compute-heavy ones. Fully populated channels with matched DIMMs keep bandwidth uniform. The board memory guide sets 6400-capable selections for the 300 W envelope. Cluster planners should reserve headroom for host overhead before packing guests, since hypervisor memory grows with virtual machine counts.

PCIe 5.0 x128 lanes per socket with CXL 2.0 attach NVMe fleets, networking and accelerators for mixed cluster duty. Slot widths follow the board design with exact splits in the manual for each chassis variant. CXL expanders add capacity tiers for hosts whose datasets exceed DIMM limits during peak quarters.

Cooling at 300 W uses vendor-qualified air or liquid heatsinks per chassis with validated airflow paths. No tray cooler ships with this mainstream virtualization processor class. Standard 2U air cooling usually covers this class well, while 1U bodies need the vendor high-performance sink selected for the chassis.

Upgrade paths

Within SP5 the 9455 grows from the 36-core AMD EPYC 9365 for threads or trims from the 64-core AMD EPYC 9555 for cost, reusing boards and memory. Each move needs only a BIOS check with matching cooling. Power capping policies deserve a recheck after any swap. Refresh cycles normally align with support contracts, so clusters upgrade on a predictable cadence. Operators planning rolling refreshes should stage one rack at a time to keep capacity online.

Frequency-optimized F SKUs serve per-core speed on the same boards at higher power for licensed database tiers. A full platform exit waits for post-SP5 sockets with fresh memory qualification.