AMD EPYC 9475F socket: SP5

What the EPYC 9475F is

The EPYC 9475F is a 48-core, 96-thread frequency-optimized server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.65 GHz base with boost to 4.8 GHz and all-core boost at 4.4 GHz. Shared L3 cache totals 256 MB. Default TDP is 400 W configurable between 320 and 400 W.

The F suffix marks frequency-optimized bins for electronic design, virtual desktops and licensed databases where per-core speed decides throughput. Against the 48-core AMD EPYC 9455 at 300 W the 9475F spends power for 500 MHz more base clock and 400 MHz more boost for faster job completion. Against the 32-core AMD EPYC 9375F it adds 16 threads at slightly lower clocks for mixed speed and density in one socket.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 3.65 GHz base is the highest sustained clock among the 48-core options, which shows in long compilation and simulation runs that never leave boost-adjacent frequencies even under full load.

Workload fit blends speed with thread count: EDA farms that parallelize across dozens of cores without sacrificing per-thread pace, plus VDI brokers serving power users. Operators pick the 9475F where the 9275F runs out of threads and dense SKUs clock too low for the license model in use every day.

Socket and motherboard compatibility

The 9475F fits the SP5 socket in FC-LGA6096 packaging on 400 W-class server boards. Genoa boards accept it after a Turin-capable firmware update. The board maker CPU support list confirms the SKU with its minimum BIOS, and power delivery must cover the upper configurable bound with clean regulation for stable all-core runs.

One or two sockets are supported. Frequency-optimized hosts often run single-socket to simplify per-core licensing, adding the second socket where thread count matters beside speed for mixed EDA batches. Memory at 12 channels feeds the fast cores without bottlenecks in either layout for consistent results across batches.

Cooling qualification belongs early at these clocks: sustained 3.65 GHz base operation assumes the vendor high-performance heatsink. Confirm the thermal solution per chassis before committing, especially in dense 1U bodies where airflow is thinnest and ambients run high year-round.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Latency-sensitive workloads want fully populated channels with matched DIMMs, since consistent interleaving beats capacity for speed in EDA jobs. The board memory guide sets 6400-capable selections. Simulation datasets should size memory for the full model footprint to avoid storage stalls during long regression sweeps.

PCIe 5.0 x128 lanes with CXL 2.0 attach NVMe, fabrics and accelerators directly to the CPU. Low-latency fabrics attach to CPU lanes for the shortest paths in trading and simulation clusters running around the clock. Board manuals define slot wiring and sharing rules per chassis for accurate deployment planning and cable routing.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks for sustained EDA duty. No tray cooler ships. Dense chassis need careful qualification at this power with these clocks, so log sustained clocks under the real mix before production use and tape-out deadlines.

Upgrade paths

Within SP5 the 9475F steps up from the 48-core AMD EPYC 9455 for clocks at higher power, or from the 32-core AMD EPYC 9375F for threads in mixed virtualization duty. Boards and memory carry over with matching cooling for faster licensed throughput. Operators should re-benchmark licensed throughput after any move, since clocks and threads trade differently per application and tool version.

Moving to dense SKUs such as the AMD EPYC 9555 trades speed for threads on the same platform for throughput-oriented clusters and batch farms. Platform exits wait for later sockets with fresh memory qualification across the data hall.