AMD EPYC 9335 socket: SP5

What the EPYC 9335 is

The EPYC 9335 is a 32-core, 64-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.0 GHz base with boost to 4.4 GHz and all-core boost at 4.0 GHz. Shared L3 cache totals 128 MB across four compute dies. Default TDP is 210 W configurable between 200 and 240 W, the efficiency end of this batch for edge duty.

Low power with high boost is the design point: 4.4 GHz peak matches bigger SKUs for bursty work while 210 W keeps sustained draw modest. Against the 36-core AMD EPYC 9365 it gives up four cores for lower watts per socket. Against the 24-core class below it keeps more threads for guests without leaving the efficient envelope. Four CCDs keep the die configuration simple, which helps consistent latency across the socket.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Edge sites and branch virtualization hosts value the 210 W rating because cooling and power budgets there run tight. Configurable TDP down to 200 W fits constrained feeds without a SKU change.

Socket and motherboard compatibility

The 9335 fits the SP5 socket in FC-LGA6096 packaging on 210 W-class server boards. Genoa boards accept it after a Turin-capable firmware update. The board maker CPU support list confirms the SKU with the minimum BIOS. Power delivery on qualified boards assumes the 240 W upper bound with margin for transients.

One or two sockets are supported. Efficient SKUs like this one pair well with compact chassis and telecom cabinets where power feeds limit bigger chips. Dual-socket layouts double cores while staying near 420 W for both processors, which fits capped power feeds. Operators with capped racks fit more 9335 hosts per row than with 300 W silicon.

Single-socket edge boards take this SKU directly. The socket and memory generation match the rest of Turin, so mixing efficient and dense SKUs across a fleet shares spares and firmware. Remote management through the board BMC covers sites without local staff.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Per-core bandwidth at 32 cores is ample, which flatters memory-bound analytics on efficient hosts. Even channel population remains the rule for full speed. Edge hosts that cache content locally should size DIMMs for the working set first, since storage speed matters less once data sits in fast RAM.

PCIe 5.0 x128 lanes with CXL 2.0 serve NVMe, networking and accelerators. Edge hosts often wire fewer slots, but the CPU lane budget stays full for chassis that need it. Board manuals set the exact splits. A single fast NIC plus boot NVMe covers most branch deployments with lanes to spare.

Cooling at 210 W fits standard air heatsinks in most chassis. No tray cooler ships. This is the easiest Turin class in the batch to cool, which is part of its appeal for remote sites with simple maintenance. Operators should still validate sustained clocks under summer ambient conditions before signing off.

Upgrade paths

Within SP5 the 9335 grows from smaller efficient SKUs or trims down from the 36-core AMD EPYC 9365 for power limits, reusing boards and memory. The 48-core AMD EPYC 9455 above adds threads at 300 W for denser guests. BIOS checks cover each move. Operators should revalidate power capping policies after any swap, since cTDP bands differ across the stack.

Frequency-optimized F SKUs such as the AMD EPYC 9175F serve per-core speed on the same boards at higher power. Platform exits wait for later sockets. Refresh planning normally follows warranty terms, so efficient hosts often serve a full second life at the edge after datacenter duty.