AMD EPYC 9015 socket: SP5

What the EPYC 9015 is

The EPYC 9015 is an 8-core, 16-thread server processor that AMD released on October 10, 2024 as the entry SKU of Turin. Zen 5 cores run at 3.6 GHz base with boost to 4.1 GHz and all-core boost at 3.95 GHz. Shared L3 cache totals 64 MB across two compute dies. Default TDP is 125 W configurable between 120 and 155 W. A note on sources: some retailer tables print 155 W, but AMD and the database agree on 125 W default, which this page follows.

Small core count with full platform I/O is the proposition: the same 12 memory channels and 128 PCIe lanes as the biggest Turin SKUs behind only 8 cores. Infrastructure roles such as firewalls, storage controllers and management hosts buy platform longevity rather than threads. The embedded twin AMD EPYC Embedded 9015 serves industrial carriers. Two CCDs keep the configuration simple with uniform latency across all cores.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs provide correction. High 3.6 GHz base clocks keep single-threaded infrastructure tasks responsive. Configurable TDP up to 155 W covers chassis with stronger cooling where sustained boost matters.

Socket and motherboard compatibility

The 9015 fits the SP5 socket as an FC-LGA6096 part on low-power server boards. Genoa boards accept it with Turin-capable firmware. The board maker CPU support list confirms the SKU with the minimum BIOS. Power delivery on qualified boards covers the 155 W upper bound with margin for transients and warm ambients.

One or two sockets are supported, though entry SKUs usually serve single-socket builds where the second socket would sit idle. Full 12-channel memory and 128 lanes stay available even here, so I/O-heavy infrastructure loses nothing to bigger SKUs. Management and hyperconverged clusters often standardize on the 9015 for lightweight nodes beside dense compute hosts.

Buyers standardizing fleets on SP5 use the 9015 for lightweight roles beside dense SKUs such as the AMD EPYC 9555 for guests. Shared socket, memory and firmware simplify spares across both. Remote sites benefit from the low thermal output, which keeps small rooms and branch closets within cooling limits.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Entry hosts rarely populate fully, but the channels exist for storage caches that grow over time. Even population keeps bandwidth uniform. Deduplication and compression tables in storage roles reward capacity planning up front, since cache hit rates decide array performance.

PCIe 5.0 x128 lanes with CXL 2.0 give storage controllers and network appliances the full Turin I/O budget. Few entry boards wire every lane, yet HBAs and NICs never wait on the CPU here. Board manuals define the fitted slots. A pair of fast NICs plus boot NVMe covers most infrastructure builds with lanes to spare.

Cooling at 125 W uses standard air heatsinks. No tray cooler ships. This is the simplest Turin class to cool in the batch, fitting quiet office-adjacent racks and branch closets. Operators should still confirm sustained boost under their own ambient conditions before signing off.

Upgrade paths

Within SP5 the 9015 is the starting rung: the 16-core AMD EPYC 9115 above doubles threads at the same 125 W for growing infrastructure. Larger jumps to the AMD EPYC 9335 add cores with higher power. Boards and memory carry over with a BIOS check. Operators should recheck power feeds before any jump, since higher SKUs assume stronger delivery.

Because the socket and I/O stay constant, in-place upgrades only need power and cooling headroom. Platform exits wait for later sockets. Infrastructure hosts often serve a full depreciation cycle before any socket change, which favors starting small on a long-lived platform.