AMD EPYC 9745 socket: SP5

What the EPYC 9745 is

The EPYC 9745 is a 128-core, 256-thread dense server processor that AMD released on October 10, 2024 with the Turin family. Zen 5c compact cores run at 2.4 GHz base with boost to 3.7 GHz and all-core boost at 3.45 GHz. Shared L3 cache totals 256 MB. Default TDP is 400 W configurable between 320 and 400 W.

Zen 5c packs 16 cores with 32 MB of L3 per die on TSMC 3 nm, against 8 cores per die on classic Zen 5. That density explains the cache math: 128 compact cores share 256 MB where 128 classic cores on the AMD EPYC 9755 enjoy 512 MB. Same ISA with full AVX-512 keeps software compatibility across both, so guests migrate freely between dense and classic hosts without rebuilds.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Lower clocks with more threads suit scale-out clouds where per-thread speed matters least for total throughput. The embedded twin AMD EPYC Embedded 9745 serves industrial carriers.

Workload fit is thread-first hosting: web fleets, container platforms and CI grids where core count decides capacity. Operators pick the 9745 over the 9755 where 128 threads suffice at lower power and cost, saving the 500 W classic SKU for cache-hungry databases and latency-sensitive primaries.

Socket and motherboard compatibility

The 9745 fits the SP5 socket in FC-LGA6096 packaging on 400 W-class server boards. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and power stages assume the full envelope with margin.

One or two sockets are supported. Dense 128-core hosts suit cloud builders who sell threads by the thousand with predictable margins: two sockets give 256 cores with 24 memory channels for the largest tenants. Per-core licensing rarely applies here, since dense hosts target unlicensed scale-out work with straightforward billing.

Boards carried over from Genoa need Turin stepping confirmation per revision before any production deployment at scale. Mixed fleets of dense Zen 5c and classic Zen 5 hosts share firmware trains, spares and management tooling across both core types every generation.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 128 cores the memory per core is thin, so fully populated high-capacity DIMMs matter more here than on smaller SKUs. The board memory guide sets legal mixes for the 400 W envelope and 2DPC fallbacks for capacity builds.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across one or two CPUs. Dense hosts often attach the most drives per socket in the fleet, and lane planning should reserve paths for every device. CXL expanders add slower tiers where datasets exceed DIMM capacity.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks matched to chassis height. No tray cooler ships. Lower per-core clocks ease hotspot intensity against classic SKUs, though total socket power matches them watt for watt.

Upgrade paths

Inside SP5 the 9745 grows from smaller dense SKUs or from classic mid-range parts for threads, keeping boards and memory with a BIOS check while power steps to 400 W. The 128-core classic AMD EPYC 9755 above doubles cache with higher clocks at 500 W for cache-hungry guests and databases. Larger dense options such as the AMD EPYC 9965 add threads at higher power for hyperscale tenants.

Leaving SP5 entirely waits for later sockets with fresh memory qualification. Dense hosts often serve web fleets for full depreciation cycles before any socket change, which favors starting on a long-lived platform with proven firmware.