AMD EPYC 9655 socket: SP5

What the EPYC 9655 is

The EPYC 9655 is a 96-core, 192-thread server processor that AMD released on October 10, 2024 as the dual-socket density option of Turin. Zen 5 cores run at 2.6 GHz base with boost to 4.5 GHz and all-core boost at 4.1 GHz. Shared L3 cache totals 384 MB across twelve compute dies of about 70.6 sq mm each. Default TDP is 400 W configurable between 320 and 400 W.

It is the 2P twin of the single-socket AMD EPYC 9655P with matching cores, clocks, cache and power. Cloud and virtualization hosts that scale to two sockets choose the 9655 for 384 threads per system, while 1P-only builds take the P SKU on cheaper boards. The embedded twin AMD EPYC Embedded 9655 serves industrial carriers. Twelve CCDs keep topology uniform for NUMA-aware guests. Operators often split sockets by workload tier, with latency-sensitive guests pinned to one socket and batch work on the other.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. High 4.5 GHz boost answers interactive work while the 2.6 GHz base holds efficiency under full-socket loads. Configurable TDP lets operators cap rack power without changing SKUs. Per-socket power monitoring keeps dense racks inside provisioned feeds during peak seasons.

Socket and motherboard compatibility

The 9655 fits the SP5 socket in FC-LGA6096 packaging on dual-capable server boards with 400 W delivery. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and power stages plus retention hardware assume the full envelope.

One or two sockets per system are supported. Dual-socket layouts deliver 192 cores with 24 memory channels for the densest guests, while single-socket use keeps licensing simple. Memory bandwidth per core stays identical either way at 12 channels per socket.

Boards carried over from Genoa need Turin stepping confirmation per revision. Mixed fleets of 9655 and P-series hosts share firmware trains, spares and management tooling across both socket counts.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket, or 12 TB in a filled pair. Dense hosts need capacity planning first: guest counts usually hit memory ceilings before thread limits. Fully populated channels with matched DIMMs keep bandwidth uniform for 96 cores. The board memory guide sets 6400-capable selections and 2DPC fallbacks. Cloud hosts that oversubscribe memory should track ballooning rates before adding guests.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across both CPUs. Inter-socket links balance traffic for guests that span sockets, though most hypervisors pin guests per socket. Board manuals define slot wiring per CPU. CXL expanders add a slower tier for cold data without new sockets.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks matched to chassis height. No tray cooler ships. Dual-socket 2U designs need careful airflow balancing between both processors, so follow the vendor thermal manual for heatsinks and shrouds.

Upgrade paths

Inside SP5 the 9655 is near the ceiling for dual-socket Turin threads, so upgrades arrive from smaller SKUs such as the 64-core AMD EPYC 9555 when guest density becomes the limit. Boards, memory and cards stay while power rises to 400 W with matching cooling. Cache grows from 256 MB to 384 MB in the same step. Operators should revalidate backup windows after consolidation, since fewer hosts carry more guests each.

Single-socket-only sites take the AMD EPYC 9655P instead at matching specs for simpler deployment. Leaving SP5 entirely waits for later sockets with fresh memory qualification and new board designs.