AMD EPYC 9845 socket: SP5

What the EPYC 9845 is

The EPYC 9845 is a 160-core, 320-thread dense server processor that AMD released on October 10, 2024 with Turin. Zen 5c compact cores on TSMC 3 nm run at 2.1 GHz base with boost to 3.7 GHz and all-core boost at 3.25 GHz. Shared L3 cache totals 320 MB. Default TDP is 390 W configurable between 320 and 400 W.

It is the second-densest Turin SKU behind the 192-core AMD EPYC 9965: 32 fewer cores at 110 W less default power for racks provisioned under the flagship envelope with room to spare. Against the 144-core AMD EPYC 9825 nearby it adds 16 cores with slightly less cache for denser tenants and longer queues. Same ISA with full AVX-512 keeps guests portable across the dense line without rebuilds or revalidation.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 2.1 GHz base is the lowest sustained clock in this batch, which suits hosts whose tenants sleep more than they compute during off-peak hours. The embedded twin AMD EPYC Embedded 9845 serves industrial carriers with long availability windows and carrier qualification.

Workload fit is dense cloud hosting at scale: container platforms, web fleets and CI grids where 320 threads per socket decide capacity. Operators pick the 9845 where the 9965 exceeds rack power but 144 cores leave threads on the table. Mid-size hyperscalers often standardize here because per-socket density stays high without flagship power provisioning.

Socket and motherboard compatibility

The 9845 fits the SP5 socket in FC-LGA6096 packaging on boards covering the 320 to 400 W band for dense duty. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS.

One or two sockets are supported. Dual-socket pairs deliver 320 cores with 24 memory channels for the largest scale-out tenants outside the flagship class with headroom to spare, while single-socket use contains licensing. Memory per thread stays thin, so capacity planning decides what fits per host.

Boards need solid power stages with heatsinked delivery for sustained operation near 390 W across long batch windows. Confirm Turin stepping per board revision and follow the vendor thermal manual for heatsink, shroud and airflow direction in dense 160-core racks.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 160 cores the memory per thread demands high-capacity DIMMs to keep tenants comfortable during peak concurrency and batch windows. Fully populated channels with matched parts keep bandwidth uniform. The board memory guide sets legal mixes for the configurable envelope and 2DPC fallbacks.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across one or two CPUs. Dense hosts attach many endpoints per socket, and lane planning should reserve paths for every device from the start of the design.

Cooling at 390 W uses vendor-qualified high-performance air or liquid heatsinks matched to chassis height. No tray cooler ships. Lower per-core clocks spread heat evenly across ten dies, though total socket power needs full qualification for continuous duty.

Upgrade paths

Inside SP5 the 9845 grows from the 144-core AMD EPYC 9825 for threads or trims from the 192-core AMD EPYC 9965 for power, reusing boards and memory with a BIOS check. Each move needs matching cooling for the envelope. Tenant density targets deserve revalidation after any swap between density classes with different cache ratios.

The classic-core alternative is the 128-core AMD EPYC 9755 with more cache per thread at higher power for database-heavy tenants. Leaving SP5 entirely waits for later sockets with fresh memory qualification for hyperscale refresh cycles.