AMD EPYC 9575F socket: SP5

What the EPYC 9575F is

The EPYC 9575F is a 64-core, 128-thread frequency-optimized server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 3.3 GHz base with boost to 5.0 GHz and all-core boost at 4.5 GHz, the highest boost in this batch. Shared L3 cache totals 256 MB across eight compute dies. Default TDP is 400 W configurable between 320 and 400 W.

The F suffix marks frequency-optimized bins purpose-built as AI host CPUs: feeding GPUs with high single-thread speed for data preparation beside accelerators. Against the 64-core AMD EPYC 9555 at 360 W the 9575F trades power for far higher clocks with matching cache. Against the 16-core AMD EPYC 9175F it keeps similar boost philosophy with four times the threads.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 5.0 GHz boost leads the Turin launch stack and shows in feed-handling and preprocessing pipelines that gate GPU throughput daily.

Workload fit is AI host duty first: GPU nodes where preprocessing speed decides accelerator use, plus licensed databases that pay per core. Operators size 9575F fleets by GPU count rather than thread count, since each host exists to keep its accelerators fed without idle gaps day and night.

Workload fit is AI host duty first and licensed speed second: GPU nodes that starve without fast preprocessing, plus databases and trading systems that pay per core. Operators size 9575F fleets by accelerator count rather than thread count, since each host exists to keep its GPUs fed around the clock.

Socket and motherboard compatibility

The 9575F fits the SP5 socket in FC-LGA6096 packaging on 400 W-class server boards, commonly GPU host nodes with accelerator wiring. Genoa boards accept it after a Turin-capable firmware update. The board maker CPU support list confirms the SKU with its minimum BIOS, and power delivery must cover the upper configurable bound.

One or two sockets are supported. AI host nodes often run single-socket beside multiple GPUs to keep feed paths short, adding the second socket where CPU threads gate throughput. Memory at 12 channels feeds preprocessing without bottlenecks in either layout.

Cooling qualification belongs early at these clocks with GPU heat in the same chassis: sustained 3.3 GHz base operation assumes the vendor high-performance heatsink with directed airflow across the CPU zone. Confirm the thermal solution per node before committing.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. Host-node duty wants fully populated channels with matched DIMMs, since data staging bandwidth decides GPU throughput as much as clocks do.. The board memory guide sets 6400-capable selections for the 400 W envelope.

PCIe 5.0 x128 lanes with CXL 2.0 attach GPUs, NVMe and fabrics directly to the CPU. Host nodes wire wide accelerator slots first, with storage and networking on remaining lanes for balanced throughput. Board manuals define the GPU slot topology per node for balanced feed paths and predictable training performance.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks. No tray cooler ships. GPU-adjacent CPU thermals need system-level validation, since accelerator exhaust raises inlet temperatures for the processor heatsink during long training runs.

Upgrade paths

Within SP5 the 9575F is the high-boost 64-core answer: buyers step here from the AMD EPYC 9555 when feed speed gates accelerators, accepting higher power. The 72-core AMD EPYC 9565 nearby adds threads at lower boost for mixed duty and batch analytics. Boards and memory carry over with matching cooling.

Moving to dense SKUs trades boost for threads on the same platform for throughput-oriented clusters. Platform exits wait for later sockets with fresh memory qualification across the entire fleet.