AMD EPYC 9825 socket: SP5

What the EPYC 9825 is

The EPYC 9825 is a 144-core, 288-thread dense server processor that AMD released on October 10, 2024 with Turin. Zen 5c compact cores on TSMC 3 nm run at 2.2 GHz base with boost to 3.7 GHz and all-core boost at 3.3 GHz. Shared L3 cache totals 384 MB. Default TDP is 390 W configurable between 320 and 400 W.

It sits between the 128-core dense AMD EPYC 9745 and the 192-core flagship AMD EPYC 9965: more threads than the former with matching cache depth for growing tenant counts, fewer cores than the latter at lower power for racks with strict thermal budgets. The 390 W rating fits chassis qualified below the 500 W class while keeping 288 threads per socket for growth. Same ISA with full AVX-512 keeps guests portable across all three density tiers without rebuilds.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Lower 2.2 GHz base clocks sip power at idle while 3.7 GHz boost answers interactive tenants without delay during peaks. Configurable TDP down to 320 W fits racks provisioned under the flagship envelope with room to spare for growth.

Workload fit is dense hosting without flagship power: clouds that want 288 threads per socket inside 400 W-capable racks, plus container platforms scaling by thread count. Operators pick the 9825 where the 9965 exceeds power budgets but 128 cores fall short on density. Mid-size clouds often standardize on this middle density because per-rack thread counts stay predictable for capacity planners year after year.

Socket and motherboard compatibility

The 9825 fits the SP5 socket in FC-LGA6096 packaging on boards with 390 W delivery inside the 320 to 400 W band. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS.

One or two sockets are supported. Dual-socket pairs deliver 288 cores with 24 memory channels for large scale-out tenants with room to grow over time, while single-socket use contains per-socket licensing. Memory per thread stays thin, so capacity planning decides tenant sizes early in the design cycle.

Boards carried over from Genoa need Turin stepping confirmation per revision. Mixed dense and classic fleets share firmware trains, spares and management tooling across both core types for simpler operations.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 144 cores the memory per thread needs high-capacity DIMMs to keep tenants comfortable. Fully populated channels with matched parts keep bandwidth uniform. The board memory guide sets legal mixes for the configurable envelope.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across one or two CPUs. Dense hosts attach many endpoints per socket, and lane planning should reserve paths for every device from the start.

Cooling at 390 W uses vendor-qualified high-performance air or liquid heatsinks matched to chassis height. No tray cooler ships. The sub-400 W default eases qualification against the 500 W flagships while keeping most of their density for cloud tenants.

Upgrade paths

Inside SP5 the 9825 grows from the 128-core dense AMD EPYC 9745 for threads or trims from the 192-core AMD EPYC 9965 for power, reusing boards and memory with a BIOS check. Each move needs matching cooling for the envelope. Operators should revalidate tenant density targets after any swap between density classes.

The classic-core alternative is the 128-core AMD EPYC 9755 with double the cache per thread at higher power for database duty. Leaving SP5 entirely waits for later sockets with fresh memory qualification.