AMD EPYC 9184X socket: SP5

What the EPYC 9184X is

The EPYC 9184X is the 16-core entry of Genoa-X with stacked L3 for SP5 servers in June 2023. Sixteen Zen 4 cores with multithreading run at 3.55 GHz base and up to 4.2 GHz boost with 3.85 GHz all-core boost, backed by 16 MB of L2 and 768 MB of L3 through 3D V-Cache die stacking. The TSMC 5 nm package triples cache against standard Genoa 16-core parts at the same core count. Default power is 320 W for single and dual socket operation.

Large cache with high clocks suits simulation, EDA and HPC codes that reuse data sets far larger than standard L3. Sixteen cores keep licences and per-core costs down while 768 MB of L3 holds models near the cores. Twelve DDR5-4800 ECC channels feed data to 6 TB per socket, while 128 Gen5 lanes per socket feed accelerators and NVMe. The balance favours per-core throughput over thread density.

Buyers choose the 9184X for cache-sensitive throughput rather than for VM density. Standard 16-core Genoa parts cost less where cache does not bind, while 32-core and 96-core X parts add threads for larger meshes. Boards that support Genoa accept Genoa-X with a BIOS update, since the socket and platform match. The Socket vs chipset: what decides whether a CPU works guide is secondary to board firmware lists for X-part support.

Socket and motherboard compatibility

The 9184X fits SP5 on single or dual socket server boards with LGA 6096 frames. Board lists must name Genoa-X 9004X for stacked-cache support, since early Genoa BIOS builds predate X IDs. Power delivery for 320 W continuous with cTDP headroom suits 1U and 2U chassis with directed airflow.

SP5 boards wire 12 DDR5 channels per socket with two DIMMs per channel for full capacity. BMC firmware covers telemetry and updates for HPC clusters. Confirm heatsink class for 320 W with stacked cache thermals, since cache dies add heat density even at modest core counts.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB per socket feeds cache-spill traffic for large models. Channel population with interleaving supports small and large configs. ECC stays enabled for long solver runs. Validated RDIMM kits at rated speed are required for 12-channel stability.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket for accelerators, networking and NVMe. Cache-heavy nodes often pair one or two GPUs with fast NVMe scratch. Cooling needs an SP5 server sink for 320 W with front-to-back flow. All-core frequency follows cooling more than the 4.2 GHz single-core boost.

Upgrade paths

On SP5 the upward moves are the 32-core 9384X and 96-core 9684X where meshes scale across threads while keeping stacked cache. Memory expansion to 12 channels and faster NVMe scratch often help more than cores for single-model throughput. The 16-core point already holds the highest base clock in Genoa-X, so core steps trade speed for threads.

Outside Genoa-X, standard Genoa trims cost where cache does not bind, while Bergamo adds threads for cloud work on SP5. Most 9184X owners tune memory and storage first, since 768 MB of L3 already removes the main bottleneck for cache-bound codes.