AMD EPYC 9965 socket: SP5

What the EPYC 9965 is

The EPYC 9965 is a 192-core, 384-thread dense server processor that AMD released on October 10, 2024 at the top of the Turin thread count. Zen 5c compact cores on TSMC 3 nm run at 2.25 GHz base with boost to 3.7 GHz and all-core boost at 3.35 GHz. Shared L3 cache totals 384 MB. Default TDP is 500 W configurable between 450 and 500 W.

It is the densest x86 server CPU of its generation: twelve 16-core Zen 5c dies behind one I/O die, with the same ISA and full AVX-512 as classic Zen 5. Against the 128-core classic AMD EPYC 9755 it trades per-thread speed and cache for 64 more cores at the same 500 W. Against the 128-core dense AMD EPYC 9745 it adds 64 cores with more cache at higher power. The embedded twin AMD EPYC Embedded 9965 serves industrial carriers.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. With 384 threads per socket, a filled pair presents 768 threads to the scheduler for massive consolidation. Power capping down to 450 W fits constrained feeds with modest clock cost.

Workload fit is maximum density per socket: hyperscale clouds, container platforms with thousands of microservices, and HPC ensembles that scale by thread count. Operators buy the 9965 where floor space and socket licenses cost more than watts, since fewer sockets carry more work per rack.

Socket and motherboard compatibility

The 9965 fits the SP5 socket in FC-LGA6096 packaging on dual-capable boards with 500 W delivery. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and voltage regulation plus retention assume the full envelope.

One or two sockets are supported. Dual-socket 9965 pairs deliver 384 cores with 24 memory channels for the largest scale-out tenants, while single-socket use keeps per-socket licensing contained. Memory per thread runs thinner than anywhere else in Turin, so capacity planning decides what fits.

Boards need the strongest power stages with heatsinked delivery for sustained 500 W operation. Confirm Turin stepping per board revision and follow the vendor thermal manual for heatsink, shroud and airflow direction in dense racks.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 192 cores the memory per thread is the thinnest in the server line, so fully populated high-capacity DIMMs are mandatory rather than optional. The board memory guide sets legal mixes for the 500 W envelope and 2DPC fallbacks for capacity-first builds.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across both CPUs. Dense hosts often attach the most endpoints per socket in the fleet, and lane planning should reserve paths for every device. CXL memory expansion helps where datasets exceed DIMM capacity.

Cooling at 500 W needs vendor-qualified high-performance air for tall chassis or direct liquid cooling for dense racks. No tray cooler ships. Lower per-core clocks spread heat evenly across twelve dies, though total socket power matches the hottest classic SKUs watt for watt.

Upgrade paths

Inside SP5 the 9965 is the ceiling for Turin thread count: upgrades arrive from the 128-core dense AMD EPYC 9745 or classic AMD EPYC 9755 when density maxes out, keeping boards and memory with a BIOS check while power steps to 500 W. Cache per thread falls in that move, so memory-sensitive guests deserve revalidation before any production cutover.

Leaving SP5 entirely waits for later sockets with fresh memory qualification. Maximum-density hosts often serve hyperscale fleets for full depreciation cycles before any socket change is considered.