AMD EPYC 9384X socket: SP5

What the EPYC 9384X is

The EPYC 9384X is the 32-core middle of Genoa-X with stacked L3 for SP5 servers in June 2023. Thirty-two Zen 4 cores with multithreading run at 3.1 GHz base and up to 3.9 GHz boost with 3.5 GHz all-core boost, backed by 32 MB of L2 and 768 MB of L3. Four CCDs with stacked cache plus the IOD form the package on TSMC 5 nm. Default power is 320 W for single and dual socket use.

Balanced threads with large cache suit simulation and EDA jobs that scale to a point but prize data reuse. Thirty-two cores keep licence costs below 96-core flagships while 768 MB of L3 holds working sets near the cores. Twelve DDR5-4800 ECC channels feed 6 TB per socket, while 128 Gen5 lanes per socket feed accelerators and NVMe. The mix often beats higher core counts for per-core throughput.

Buyers compare the 9384X against standard 9354 where cache does not bind and against 9184X where fewer threads suffice. Boards that run Genoa accept Genoa-X with a BIOS update on the same SP5 socket. The Socket vs chipset: what decides whether a CPU works guide is secondary to board firmware lists for X-part qualification.

Socket and motherboard compatibility

The 9384X fits SP5 on single or dual socket server boards with LGA 6096 frames. Board lists must name Genoa-X 9004X for stacked-cache boot support. Power delivery for 320 W continuous suits 1U and 2U chassis with directed airflow.

SP5 boards wire 12 DDR5 channels per socket with two DIMMs per channel for full capacity. BMC firmware covers cluster updates. Confirm heatsink class for 320 W with stacked cache density before consolidating solvers.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB per socket supports large models that use cache plus memory together. Flexible channel counts tune cost and bandwidth. ECC stays enabled for long EDA runs. Validated kits at rated speed are required for stability.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket for fabric, GPUs and NVMe. A 32-core node often pairs one or two accelerators with fast scratch. Cooling needs an SP5 server sink for 320 W with front-to-back flow. Sustained clocks follow cooling more than the 3.9 GHz boost.

Upgrade paths

On SP5 the upward move is the 96-core 9684X where meshes scale across threads with stacked cache, while memory and NVMe growth often help more for single-model speed. The 32-core point balances licences and throughput, so scaling tests should guide core steps.

Outside Genoa-X, standard Genoa lowers cost where cache misses are rare, while Bergamo adds threads for cloud work on SP5. Most 9384X owners expand memory and scratch first, since 768 MB already covers many working sets.