AMD EPYC Embedded 9745 socket: SP5

What the AMD EPYC Embedded 9745 is

The AMD EPYC Embedded 9745 is the 128-core dense member of the EPYC Embedded 9005 Turin stack on Socket SP5. It runs 256 threads at 2.4 GHz base with boost to 3.7 GHz, backed by 256 MB of L3 cache and a 400 W default TDP. AMD announced the Embedded 9005 series on March 11, 2025 with production shipments expected in the second quarter of 2025, building the dense Zen 5c chiplets on a 3 nm process with a 6 nm I/O die.

One hundred twenty-eight small cores suit cloud hosts, analytics, content platforms and storage clusters that scale by threads rather than frequency. The 400 W class fits high-airflow racks without reaching for the top 500 W tier, while 256 threads absorb parallel jobs. The 256 MB L3 pool spreads across many CCDs to keep data near the cores.

Against the classic-core 128-core AMD EPYC Embedded 9755 beside it, the 9745 trades per-core speed and extra cache for lower power draw at the same core count. Against the 160-core AMD EPYC Embedded 9845 above it, the 9745 keeps a lower 400 W class for standard cooling. Long-life firmware and 7-year manufacturing support suit carrier builds. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Socket and motherboard compatibility

The 9745 fits Socket SP5, a 6,096-contact land grid array that AMD built for EPYC 9004 Genoa and EPYC 9005 Turin processors. Boards support one or two sockets with this non-P part, so one 9745 fills a dense appliance or pairs with an identical 9745 in a dual-socket node. SP5 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor.

Turin dense cores share SP5 packaging with Genoa, but firmware must know the Zen 5c topology explicitly. Only boards whose BIOS lists Turin dense parts can take the 9745, and power delivery must cover the 400 W class. Memory on a carryover board may stay at the older qualified speed rather than reaching DDR5-6000, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP5 socket feeds 12 DDR5 channels with ECC RDIMM or 3DS RDIMM modules, and AMD rates Turin to 6000 MT/s with 6400 MT/s in target configs for up to 6 TB per socket. Twelve channels keep 256 threads supplied in cloud, analytics and storage mixes. Population order and maximum capacity vary by board, so the vendor memory list governs every build, and dual-socket builds use matched DIMM populations.

PCI Express connectivity is Gen 5 with x128 lanes per socket, plus x8 Gen 3 lanes for board devices and slower slots. That lane budget feeds NVMe fleets, high-speed networking and accelerators on a dense node without lane sharing pressure. CXL 2.0 memory expansion is part of the Turin platform where the board wires it, and bifurcation follows board firmware, so architects confirm slot maps before committing to a throughput layout.

Cooling follows the board vendor list rather than a retail box. SP5 uses server retention with heatsinks validated per TDP class, and the 9745 at 400 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a site demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9745 starts with the 160-core AMD EPYC Embedded 9845 and the 192-core AMD EPYC Embedded 9965, all staying on SP5 boards where power and cooling allow. The classic-core 128-core AMD EPYC Embedded 9755 beside it trades thread density for higher clocks at 500 W. Each move keeps board and memory investments where the TDP class allows, plus a BIOS that already supports Turin.

The step down to the 96-core AMD EPYC Embedded 9655 moves back to full-size Zen 5 cores for frequency-sensitive mixes. A move to AM5 entry servers is a different platform with 2 memory channels and far lower power classes. That change replaces board, memory population and cooling design from scratch. The decision turns on threads per watt against per-core speed.