AMD EPYC 9655P socket: SP5

What the EPYC 9655P is

The EPYC 9655P is a 96-core, 192-thread server processor that AMD released on October 10, 2024 for single-socket systems. It uses Zen 5 Turin cores at 2.6 GHz base with boost to 4.5 GHz and all-core boost at 4.1 GHz. Shared L3 cache totals 384 MB across twelve compute dies of about 70.6 sq mm each. Default TDP is 400 W configurable between 320 and 400 W.

The P suffix marks single-socket platforms: the AMD EPYC 9655 matches it on cores, clocks, cache and power but scales to two sockets, while the 9655P is priced and qualified for 1P boards. Buyers who never need a second socket save on board cost and licensing tied to socket count. The embedded twin AMD EPYC Embedded 9655P serves industrial carriers. Twelve CCDs beside the central I/O die keep the topology uniform for NUMA-aware guests.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry error correction. With 192 threads in one socket, virtualization hosts consolidate many guests without NUMA hops between sockets. Configurable TDP lets operators cap sustained power for dense racks without changing SKUs.

Socket and motherboard compatibility

The 9655P fits the SP5 socket in the FC-LGA6096 package on single-socket server boards. Only 1P board designs with 400 W power delivery and cooling qualify, even though the socket matches dual-capable platforms. The board maker CPU support list confirms the SKU with its minimum BIOS. Power stages, socket retention and airflow shrouds all assume the full 400 W envelope on qualified boards.

Choosing P over non-P is a platform decision made at purchase: 1P boards cost less and simplify NUMA layout, while 2P boards with the AMD EPYC 9655 double sockets later. Memory population stays at 12 channels either way, so bandwidth per core is identical. Licensing models that charge per socket favor the P line wherever a second socket adds no value.

Boards carried over from Genoa generally accept Turin after a firmware update. Confirm Turin stepping support per board revision rather than assuming the socket alone guarantees boot. Mixed fleets of P and non-P hosts share firmware trains and management tooling.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB in one socket. Single-socket hosts lean harder on memory capacity per core, so fully populating channels matters more here than in dual-socket designs that split guests across sockets. The board memory guide sets legal DIMM mixes for the 400 W envelope. Database consolidation ratios usually hit the 6 TB ceiling before the 192-thread limit, so capacity planning comes first.

PCIe 5.0 x128 lanes with CXL 2.0 serve NVMe, networking and accelerators from the single CPU. All devices attach without inter-socket links, which keeps latency uniform. Slot bifurcation follows the 1P board layout. CXL memory expanders add a second tier for hosts whose working sets exceed DIMM capacity without adding sockets.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks for the chassis height. No tray cooler ships. Single-socket 1U designs need careful airflow qualification at this power, so follow the vendor thermal manual for the exact heatsink and shroud. Operators should validate sustained all-core clocks under their own guest mix before signing off.

Upgrade paths

Inside single-socket SP5 the 9655P is near the ceiling for Turin core count, so upgrades arrive from smaller SKUs such as the 64-core AMD EPYC 9555P when guest density becomes the limit. Board, memory and cards stay while power rises to 400 W with matching cooling.

Moving to dual-socket means new boards with the AMD EPYC 9655 instead. Leaving SP5 entirely waits for a later socket generation with fresh memory qualification.