AMD EPYC 9565 socket: SP5

What the EPYC 9565 is

The EPYC 9565 is a 72-core, 144-thread server processor that AMD released on October 10, 2024 in the Turin family. Zen 5 cores run at 3.15 GHz base with boost to 4.3 GHz and all-core boost at 4.2 GHz. Shared L3 cache totals 384 MB across twelve compute dies. Default TDP is 400 W configurable between 320 and 400 W.

It pairs the 96-core class cache with 72 faster cores: the same 384 MB as the AMD EPYC 9655 behind fewer, higher-clocked threads for mixed database and virtualization duty. Against the 64-core AMD EPYC 9555 at 360 W it adds 8 cores with more cache at higher power. Twelve CCDs carry 32 MB of L3 each for uniform guest placement.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs provide correction. The 3.15 GHz base is unusually high for this core count, which keeps sustained throughput strong where boost cannot hold across all cores.

Workload fit decides between the 9565 and its neighbors: database servers with large buffer pools love the 384 MB cache behind 72 fast cores, while virtualization hosts with thousands of small guests may prefer the 96-core AMD EPYC 9655 for thread count. Build farms and CI runners value the 3.15 GHz base most of all, since compilation holds all cores busy for minutes at a time. Operators should match the SKU to the dominant load rather than buying cores alone for vanity metrics.

Socket and motherboard compatibility

The 9565 fits the SP5 socket as an FC-LGA6096 part on 400 W-class server boards. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and power delivery must cover the upper configurable bound.

One or two sockets are supported. High-base-clock SKUs like this one suit buyers who run sustained loads rather than bursts: databases, analytics and build farms that hold all cores busy. Dual-socket layouts double the fast cores with 24 memory channels behind them.

Single-socket deployments compare P-series options for 1P boards with lower platform costs. The socket, memory generation and PCIe generation stay identical, so the choice reduces to socket count against licensing and board cost.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. With 384 MB of cache plus wide memory channels, the 9565 feeds data-hungry analytics without starving cores. Fully populated channels with matched DIMMs keep bandwidth uniform. The board memory guide sets 6400-capable selections for the 400 W envelope.

PCIe 5.0 x128 lanes per socket with CXL 2.0 attach NVMe, networking and accelerators. Slot bifurcation follows the board design, with exact splits in the manual. CXL memory expanders suit hosts whose datasets exceed DIMM capacity.

Cooling at 400 W needs vendor-qualified high-performance air or liquid heatsinks per chassis sized for sustained loads. No tray cooler ships. Sustained 3.15 GHz base operation assumes the vendor heatsink and shroud combination, not entry air, so confirm thermals per chassis before committing.

Upgrade paths

Within SP5 the 9565 sits between the 64-core AMD EPYC 9555 and the 96-core AMD EPYC 9655 on threads, with base clocks above both. Upgrades from smaller SKUs keep boards and memory with a BIOS check while power steps to 400 W. Frequency-optimized F SKUs serve per-core speed instead of threads on the same boards.

A full platform exit waits for post-SP5 sockets with fresh memory qualification. Refresh cycles normally align with warranty terms, so the socket choice outlives any single deployment.