AMD EPYC 9684X socket: SP5

What the EPYC 9684X is

The EPYC 9684X tops Genoa-X with 96 Zen 4 cores and 192 threads plus stacked L3 for SP5 servers in June 2023. Cores run at 2.55 GHz base and up to 3.7 GHz boost with 3.42 GHz all-core boost, backed by 96 MB of L2 and 1152 MB of L3 through 3D V-Cache. Twelve CCDs with 96 MB of stacked cache per die plus the IOD form the package on TSMC 5 nm. Default power is 400 W for single and dual socket operation.

Maximum threads with maximum cache suits HPC centres that run large meshes across many nodes. Ninety-six cores share 1152 MB of L3 for data reuse at scale, while 12 DDR5-4800 ECC channels feed 6 TB per socket. One hundred twenty-eight Gen5 lanes per socket feed interconnects, accelerators and NVMe. Power and cooling exceed standard Genoa flagships because stacked cache adds density.

Buyers compare the 9684X against standard 9654 where cache does not bind and against dual-socket Xeon fleets where throughput per rack matters. The X part costs more per core but cuts node counts for cache-bound jobs. Boards that run Genoa accept Genoa-X with a BIOS update on the same SP5 socket. The CPU cooler compatibility by socket guide covers why 400 W server cooling decides sustained all-core speed.

Socket and motherboard compatibility

The 9684X fits SP5 on single or dual socket server boards with LGA 6096 frames and 400 W power delivery. Board lists must name Genoa-X 9004X for stacked-cache support. Early Genoa BIOS builds do not cover X IDs, so firmware must be updated before the swap. Socket fit alone does not promise boot.

SP5 boards wire 12 DDR5 channels per socket with two DIMMs per channel for full 6 TB. BMC firmware handles cluster telemetry and updates. Builders should confirm heatsink class for 400 W with stacked cache plus PSU capacity for dual socket nodes that approach 800 W of CPU power alone.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB per socket supports large meshes that spill beyond even 1152 MB of L3. Interleaving across 2 to 12 channels tunes small and large configs. ECC stays enabled for multi-day solver runs. Validated RDIMM kits at rated speed are mandatory for 12-channel stability at 400 W.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket for fabric, accelerators and NVMe. Cache-rich nodes often pair high-radix networking with fast scratch. Cooling needs SP5 liquid or high-performance air qualified for 400 W continuous with front-to-back data-centre flow. All-core frequency follows cooling more than the 3.7 GHz boost label.

Upgrade paths

The 9684X already tops Genoa-X threads and cache, so upgrades mean memory, fabric and NVMe rather than more cores. Filling 12 channels, adding faster interconnects and expanding scratch bring the largest gains for existing owners. Downward moves to fewer X cores raise clocks for latency-sensitive models but give up throughput.

Outside Genoa-X, standard Genoa trims cost where cache does not bind, while Bergamo adds threads for cloud work on SP5. Most 9684X owners optimise cluster balance first, since 96 cores with 1152 MB already saturate many scaling ceilings.