AMD EPYC Embedded 9254 socket: SP5

What the EPYC Embedded 9254 is

The EPYC Embedded 9254 is the 24-core high-clock Genoa embedded part for SP5 in March 2023. Twenty-four Zen 4 cores with multithreading run at 2.9 GHz base and up to 4.15 GHz boost with 3.9 GHz all-core boost, backed by 24 MB of L2 and 128 MB of L3. Three CCDs plus the IOD form the package on TSMC 5 nm with a 200 W default inside a 200 to 240 W window. It targets edge nodes that need per-core speed with moderate density and long supply.

High boost with 24 cores suits network functions and control planes that prize single-thread bursts plus solid threading. Twelve DDR5-4800 ECC channels give full server bandwidth even at modest core counts, which helps buffers and images. One hundred twenty-eight Gen5 lanes per socket keep NICs and NVMe fed for single and dual socket nodes.

Buyers step to the 9254 for clocks with embedded qualification rather than for maximum threads. It shares SP5 platform with larger Genoa parts, so scaling to 32 cores stays on the same board where power allows. Smaller control nodes stay with 16 cores. The Socket vs chipset: what decides whether a CPU works guide is secondary to board support lists.

Socket and motherboard compatibility

The Embedded 9254 fits SP5 on single or dual socket embedded boards with LGA 6096 frames. Board lists must name Genoa Embedded 9004. Power delivery for 200 W continuous with cTDP headroom suits compact edge chassis.

SP5 boards wire 12 DDR5 channels per socket with flexible populations. BMC firmware covers remote management. Confirm heatsink height for 1U nodes before ordering.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels per socket to 6 TB feeds 24 fast cores. Fewer channels can be populated for cost with interleaving. ECC stays enabled for edge uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket plus CXL. A 24-core node typically wires NICs and NVMe arrays with lanes to spare. Cooling needs an SP5 sink for 200 W with front-to-back flow.

Upgrade paths

On SP5 the upward moves are 32-core and higher Genoa embedded parts where VM counts grow, without changing boards where power allows. Memory and NIC additions often help more than cores for port growth. The 24-core point keeps clocks highest among midrange embedded parts.

Outside SP5, Siena on SP6 lowers power for telco edge, while higher Genoa counts add density on SP5. Most Embedded 9254 owners add IO first.