AMD EPYC Embedded 9124 socket: SP5

What the EPYC Embedded 9124 is

The EPYC Embedded 9124 is the 16-core entry of Genoa embedded for SP5 systems in March 2023. Sixteen Zen 4 cores with multithreading run at 3.0 GHz base and up to 3.7 GHz boost with 3.6 GHz all-core boost, backed by 16 MB of L2 and 64 MB of L3. Two CCDs plus the IOD form the package on TSMC 5 nm with a 200 W default inside a 200 to 240 W window. It suits edge nodes that need high clocks with modest core counts and long supply.

High base clock with 16 cores favours latency-sensitive network functions and control planes that do not scale to dozens of cores. Twelve DDR5-4800 ECC channels give full server bandwidth even at low core counts, which helps packet buffers and VM images. One hundred twenty-eight Gen5 lanes per socket keep NICs and NVMe fed for single-socket edge boxes.

Buyers step to the 9124 for per-core speed with embedded qualification rather than for density. It matches the server 9124 in silicon but adds lifecycle for multi-year edge fleets. Workloads that outgrow 16 cores move to 24-core or 32-core Genoa embedded parts on the same SP5 base. The Socket vs chipset: what decides whether a CPU works guide matters less than board firmware lists for server fit.

Socket and motherboard compatibility

The Embedded 9124 fits SP5 on single or dual socket embedded boards with LGA 6096 frames. Board lists must name Genoa Embedded 9004 for boot support. Power delivery for 200 W continuous with lower cTDP options suits compact edge chassis that cannot cool 360 W flagships.

SP5 boards wire 12 DDR5 channels per socket with options for 2 to 12 channel populations. BMC management covers remote update for far-flung nodes. Confirm heatsink height and airflow for 1U and short-depth chassis before ordering.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB per socket feeds 16 cores with ample headroom. Small configs can run with fewer channels and interleave for cost control. ECC stays on for edge uptime. Validated kits at rated speed are the correct choice over faster desktop memory.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket plus CXL for accelerators. A 16-core node typically wires several NICs and NVMe arrays with lanes to spare. Cooling needs an SP5 server sink for 200 W with front-to-back flow. Lower cTDP settings trim clocks for hot closets.

Upgrade paths

On SP5 the upward moves are 24-core, 32-core and higher Genoa embedded parts where session counts grow, without changing boards where power allows. Memory expansion to more channels and NIC additions often help more than cores for port density. The 16-core starting point keeps clocks high, so core steps trade speed for threads.

Outside SP5, Siena on SP6 lowers power for telco edge, while higher Genoa counts add density on SP5. Most Embedded 9124 owners add IO first, since 16 fast cores already cover control-plane duty.