AMD EPYC Embedded 9554P socket: SP5

What the EPYC Embedded 9554P is

The EPYC Embedded 9554P is the 64-core single socket Genoa embedded part for SP5 in March 2023. Sixty-four Zen 4 cores with multithreading run at 3.1 GHz base and up to 3.75 GHz boost with matching all-core boost, backed by 64 MB of L2 and 256 MB of L3. Eight CCDs plus the IOD form the package on TSMC 5 nm with a 360 W default inside a 320 to 400 W window. The P suffix marks single socket operation, so dual socket pairing is not supported.

High core count with high clocks suits consolidated edge clouds that pack virtual machines and network functions into one chassis. Sixty-four cores share 256 MB of L3 for VM density, while 12 DDR5-4800 ECC channels feed data to 6 TB. One hundred twenty-eight Gen5 lanes serve NICs, accelerators and NVMe without a second socket. Single socket design trims board cost and power against 2P systems.

Buyers choose the P variant for single-socket edge nodes where a second socket would waste power and slots. It matches the 9554 in clocks and cache but locks to 1P operation for qualified embedded supply. Workloads that exceed 64 cores step to 96-core embedded parts on the same SP5 base. The Socket vs chipset: what decides whether a CPU works guide is secondary to board support lists for P-part fit.

Socket and motherboard compatibility

The Embedded 9554P fits SP5 on single socket embedded boards with LGA 6096 frames. Dual socket boards do not accept P parts for 2P operation, so the board list must name the P variant explicitly. Power delivery for 360 W continuous with cTDP options suits single-socket edge chassis with strong airflow.

SP5 single socket boards wire 12 DDR5 channels with two DIMMs per channel for full capacity. BMC firmware covers remote management for edge sites. Confirm heatsink and PSU sizing for sustained all-core loads before consolidating VMs.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB feeds 64 cores for VM density. Flexible 2 to 12 channel populations support small and large configs with interleaving. ECC stays enabled for edge uptime. Validated RDIMM kits at rated speed are required for signal integrity at 12 channels.

PCIe Gen5 gives 128 lanes in single socket plus CXL and SATA for board devices. Typical wiring feeds multiple NICs, accelerators and NVMe arrays. Cooling needs an SP5 server sink for 360 W with front-to-back flow. Lower cTDP settings help hot edge closets at the cost of clocks.

Upgrade paths

On SP5 single socket the upward move is the 96-core Embedded 9654P for maximum density without adding sockets. Memory growth to 12 channels and NIC or NVMe additions often help more than cores for consolidation. The 64-core point already balances clocks and threads, so scaling tests should guide core steps.

Outside single socket SP5, dual socket Genoa adds sockets for larger fabrics, while Siena on SP6 lowers power for telco edge. Most Embedded 9554P owners expand memory and IO on SP5 first, since 64 fast cores cover heavy edge clouds.