AMD EPYC Embedded 9454 socket: SP5

What the EPYC Embedded 9454 is

The EPYC Embedded 9454 is the 48-core dual socket capable Genoa embedded part for SP5 in March 2023. Forty-eight Zen 4 cores with multithreading run at 2.75 GHz base and up to 3.8 GHz boost with 3.65 GHz all-core boost, backed by 48 MB of L2 and 256 MB of L3. Six CCDs plus the IOD form the package on TSMC 5 nm with a 290 W default inside a 240 to 300 W window. It supports single and dual socket operation for scalable edge fabrics.

Balanced density with dual socket option suits edge clusters that scale from one to two sockets per node. Forty-eight cores per socket give 96 cores in 2P with shared memory pools, while 12 DDR5-4800 ECC channels per socket feed 6 TB each. One hundred twenty-eight Gen5 lanes per socket and up to 160 in 2P feed fabric, accelerators and NVMe. Power stays moderate against 360 W flagships.

Buyers choose the non-P 9454 for socket flexibility where nodes may grow to 2P later. It matches the 9454P in clocks and cache but allows dual socket pairing for larger fabrics. Smaller nodes stay with fewer cores on the same SP5 base. The Socket vs chipset: what decides whether a CPU works guide is secondary to board firmware lists.

Socket and motherboard compatibility

The Embedded 9454 fits SP5 on single or dual socket embedded boards with LGA 6096 frames. Board lists must name Genoa Embedded 9004 for boot support. Power delivery for 290 W per socket with cTDP options suits scalable edge chassis.

SP5 boards wire 12 DDR5 channels per socket with two DIMMs per channel for full capacity. BMC firmware covers cluster management. Confirm heatsink, PSU and airflow for 2P nodes that approach 580 W of CPU power.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels per socket to 6 TB feeds 48 cores per socket. Flexible populations support cost control. ECC stays enabled for edge uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket plus CXL. Typical 2P wiring feeds fabric, accelerators and NVMe arrays. Cooling needs SP5 server sinks for 290 W per socket with front-to-back flow.

Upgrade paths

On SP5 the upward moves are 64-core and 96-core Genoa embedded parts where density grows, or adding a second 9454 socket where boards allow 2P. Memory growth to 12 channels per socket and fabric additions often help more than cores. The 48-core point balances density and power.

Outside SP5, Siena on SP6 lowers power for telco edge, while Genoa-X adds cache on SP5. Most Embedded 9454 owners scale sockets and IO first.