AMD EPYC 8024PN socket: SP6

What the EPYC 8024PN is

The EPYC 8024PN is the 8-core NEBS variant of Siena for SP6 in September 2023. Eight Zen 4c small cores with multithreading run at 2.05 GHz base and up to 3.0 GHz boost with 2.95 GHz all-core boost, backed by 8 MB of L2 and 32 MB of L3. The TSMC 5 nm package targets 80 W with no configurable TDP window in AMD listings. The PN suffix marks Network Equipment Building System compliance for -5 to 85 C operation against 0 to 75 C on P parts.

Low power with server IO suits telco curbside, retail and outdoor edge boxes that face wide temperatures. Eight cores handle gateway, IoT aggregation and entry storage at low noise, while 6 DDR5-4800 ECC channels keep board cost down. Ninety-six Gen5 lanes serve networking and NVMe for single-socket designs. NEBS tolerance matters more than peak clocks for curbside deployment.

Buyers compare the 8024PN against P parts where wider temperature and NEBS paperwork matter. Clocks match NEBS limits with a lower 2.05 GHz base against higher P bases, while boost still reaches 3.0 GHz. Boards built for SP6 accept PN parts with a BIOS update. The Socket vs chipset: what decides whether a CPU works guide is secondary to SP6 NEBS board lists.

Socket and motherboard compatibility

The 8024PN fits SP6 on single socket NEBS boards with LGA 4844 frames. Siena is 1P-only, so dual socket pairing is not supported. Board lists must name Siena 8004 PN for NEBS temperature support. Power delivery for 80 W continuous suits fan-leaning outdoor enclosures.

SP6 NEBS boards wire 6 DDR5 channels with rugged thermals for -5 to 85 C. BMC firmware covers remote management for unmanned sites. Confirm heatsink and enclosure rating for dust and heat before curbside deployment.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 6 channels feeds 8 small cores for gateway work. Capacity scales with large DIMMs for storage nodes. ECC stays enabled for unmanned uptime. Validated NEBS kits at rated speed are required.

PCIe Gen5 gives 96 lanes in single socket plus CXL for networking and NVMe. An 8-core node typically wires several NICs and NVMe arrays. Cooling needs an SP6 sink for 80 W with wide-temperature validation. Lower power allows smaller fans and better acoustics.

Upgrade paths

On single socket SP6 the upward moves are 16-core and higher Siena parts where vCPU counts grow, without adding sockets. Memory growth to 6 channels and networking additions often help more than cores. The 8-core PN point already covers gateway duty at minimal power.

Outside Siena, Genoa on SP5 adds channels and sockets for larger fabrics. Most 8024PN owners expand IO on SP6 first, since NEBS qualification matters more than core counts for curbside fleets.