AMD EPYC 8534P socket: SP6

What the EPYC 8534P is

The EPYC 8534P tops the Siena line with 64 Zen 4c small cores and 128 threads for single socket SP6 servers in September 2023. Cores run at 2.3 GHz base and up to 3.1 GHz boost with matching all-core boost, backed by 64 MB of L2 and 128 MB of L3. The TSMC 5 nm package targets 200 W inside a 155 to 225 W window for efficient racks that cannot cool 360 W Genoa parts. It is the densest Siena option for telco and edge clouds.

Efficient threads with server IO suit scale-out hosts that pack virtual machines and containers into compact nodes. Sixty-four cores share 128 MB of L3 for locality, while 6 DDR5-4800 ECC channels keep board cost down against 12-channel platforms. Ninety-six Gen5 lanes serve networking and NVMe for single-socket designs. Power per core stays low for dense deployments.

Buyers compare the 8534P against Genoa density parts where 12 channels matter and against Xeon efficiency parts where performance per watt decides. Siena wins single-socket efficiency with 6 channels, while Genoa wins where memory bandwidth dominates. Boards built for SP6 accept the full Siena stack with a BIOS update. The Socket vs chipset: what decides whether a CPU works guide is secondary to SP6 board lists.

Socket and motherboard compatibility

The 8534P fits SP6 on single socket server boards with LGA 4844 frames. Siena is 1P-only, so dual socket pairing is not supported. Board lists must name Siena 8004 for Zen 4c support. Power delivery for 200 W continuous with wide cTDP suits 1U and short-depth chassis.

SP6 boards wire 6 DDR5 channels with one DIMM per channel for best speed in many layouts. BMC firmware covers fleet management. Confirm heatsink height and airflow for dense 64-core nodes.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 6 channels feeds 64 small cores for edge clouds. Capacity scales with large DIMMs for storage nodes. ECC stays enabled for uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 96 lanes in single socket plus CXL for networking and NVMe. A 64-core node typically wires faster NICs plus NVMe arrays. Cooling needs an SP6 server sink for 200 W with front-to-back flow. Lower cTDP trims clocks for hot aisles.

Upgrade paths

The 8534P already tops Siena core counts, so upgrades mean memory, networking and NVMe rather than more cores. Filling 6 channels and adding faster NICs bring the largest gains. Downward moves trim power where 64 cores exceed needs.

Outside Siena, Genoa on SP5 adds channels and sockets for larger fabrics. Most 8534P owners expand memory and IO on SP6 first, since 64 efficient cores already cover dense single-socket hosts.