AMD EPYC 8535P socket: SP6

What the AMD EPYC 8535P is

The AMD EPYC 8535P is the 64-core high-volume model of the EPYC 8005 Sorano stack on Socket SP6. It runs 128 threads at 2.0 GHz base with boost to 4.5 GHz, backed by 256 MB of L3 cache and a 210 W default TDP. AMD announced Sorano in February 2026 and launched the stack in May 2026, building it on full Zen 5 cores with a 5nm process instead of the denser Zen 4c cores used in Siena.

Sixty-four cores at a 2.0 GHz base suit virtualization hosts, cloud storage nodes and telco user-plane functions where steady multi-thread throughput matters more than single-thread bursts. The 256 MB L3 pool spreads across the compute chiplets and keeps tenant data resident while dozens of virtual machines contend for cache. At 210 W the part sits one step below the top of the SP6 power band, so most boards qualified for the upper TDP class cover it with the vendor heatsink kit.

Against the 84-core 8635P above it, the 8535P gives up 20 cores and 128 MB of L3 for a 300 USD lower 1Ku price, namely 5499 USD, plus a 15 W lower TDP. Against the 48-core 8435P below it, it offers one third more cores for heavily parallel farms while holding the same 256 MB cache size. Buyers who consolidate racks of older dual-socket hosts onto single-socket edge nodes land here. The 8535P is the capacity pick short of the flagship.

Socket and motherboard compatibility

The 8535P fits Socket SP6, a 4,844-contact land grid array that AMD built for EPYC 8004 Siena processors from 8 to 64 cores and EPYC 8005 Sorano processors from 8 to 84 cores. Every board is single-socket only, so one 8535P fills the socket and there is no second-socket upgrade to plan. SP6 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Sorano is a drop-in replacement on Siena boards after a BIOS update from the board maker, at the same power class. The 8535P at 210 W needs a board qualified above the old 200 W Siena ceiling, so the vendor support list decides each swap. Memory on a converted board may stay at the Siena qualified speed rather than reaching DDR5-6400. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP6 socket feeds 6 DDR5 channels with ECC RDIMM modules, and AMD rates Sorano to 6400 MT/s for up to 3 TB per socket. Six channels at these rates keep 128 threads supplied in virtualization and analytics mixes with high memory pressure. Population order, maximum capacity and per-board speed caps vary, so the vendor memory list governs every build. Where a Siena board caps speeds lower, bandwidth-bound tenants feel the limit first.

PCI Express connectivity is Gen 5 with x96 lanes per socket, plus x8 Gen 3 lanes that carry board devices and slower slots. That lane budget feeds NVMe shelves, high-speed networking and accelerators on a single-socket board without the lane sharing compromises of smaller platforms. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. CXL 2.0 memory expansion is part of the Sorano platform where the board wires it.

Cooling follows the board vendor list rather than a retail box. SP6 uses server retention with heatsinks validated per TDP class, and the 8535P at 210 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 8535P is the 84-core 8635P flagship, staying on SP6 boards with attention to its 225 W class. The path down is the 48-core 8435P or the 32-core 8325P where license costs or power envelopes favor fewer cores. Single-socket edge sites can right-size per node without touching rack layout. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP8 is a different platform with 8 memory channels, PCIe 6.0 and higher power classes, aimed at mainstream enterprise racks rather than compact edge nodes. That change replaces board, memory population and cooling design from scratch. Buyers coming from older SP5 Turin systems face the same full-platform refresh. The decision turns on whether the workload needs SP6 efficiency at the edge or mainstream rack density, and the answer differs for storage clusters and for flagship compute hosts.