AMD EPYC Embedded 8C24P socket: SP6

What the EPYC Embedded 8C24P is

The EPYC Embedded 8C24P is the 12-core Siena embedded part for single socket SP6 in September 2023. Twelve Zen 4c small cores with multithreading run at 2.45 GHz base and up to 3.0 GHz boost with 2.95 GHz all-core boost, backed by 12 MB of L2 and 32 MB of L3. The TSMC 5 nm package targets 100 W inside a 70 to 100 W window for low-power embedded nodes with long supply. AMD notes that early 8C24P data were engineering projections, with final silicon matching the listed clocks.

Few cores with full platform IO suit embedded gateways and retail nodes that need lanes and memory over threads. Twelve cores share 32 MB of L3 for locality, while 6 DDR5-4800 ECC channels keep board cost down. Ninety-six Gen5 lanes serve networking and NVMe for single-socket designs. Low power allows compact chassis with modest cooling.

Buyers choose the 8C24P for entry embedded density with server management rather than for throughput. It sits below 16-core Siena parts on the same SP6 base with lower power. Larger embedded Siena parts add threads where vCPU counts grow. The Socket vs chipset: what decides whether a CPU works guide is secondary to SP6 embedded board lists.

Socket and motherboard compatibility

The Embedded 8C24P fits SP6 on single socket embedded boards with LGA 4844 frames. Siena is 1P-only, so dual socket pairing is not supported. Board lists must name Siena Embedded 8004 for boot support. Power delivery for 100 W continuous suits compact embedded chassis.

SP6 embedded boards wire 6 DDR5 channels with one DIMM per channel for best speed in many layouts. BMC firmware covers remote management for far-flung nodes. Confirm heatsink height for short-depth nodes.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 6 channels feeds 12 small cores for gateway work. Capacity scales with large DIMMs. ECC stays enabled for uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 96 lanes in single socket plus CXL for networking and NVMe. A 12-core node typically wires NICs plus NVMe arrays with lanes to spare. Cooling needs an SP6 server sink for 100 W with compact airflow.

Upgrade paths

On single socket SP6 the upward moves are 16-core and higher embedded Siena parts where vCPU counts grow, without adding sockets. Memory growth to 6 channels and networking additions often help more than cores. The 12-core point already covers gateway duty at minimal power.

Outside Siena, Genoa embedded on SP5 adds channels and sockets for larger fabrics. Most Embedded 8C24P owners expand IO on SP6 first.