AMD EPYC 7642 socket: SP3
The AMD EPYC 7642 uses SP3, the LGA socket for EPYC server processors. The 48-core chip pairs 256 MB of cache with 225 W.
AMD EPYC 7642 specifications
| Cores | 48 |
|---|---|
| Threads | 96 |
| Core architecture | Zen 2 (Rome) |
| Clocks | 2.3 GHz base, up to 3.3 GHz boost |
| Cache | 24 MB L2 plus 256 MB L3 |
| Default TDP | 225 W |
| Manufacturing process | TSMC 7 nm FinFET |
| Memory support | DDR4-3200 ECC, 8 channels |
| PCI Express | 128 PCIe Gen4 lanes per socket, up to 160 in 2P |
| Integrated graphics | None (BMC graphics on board) |
| Multiplier | Locked |
| ECC memory | Supported, DDR4 ECC RDIMM |
| Package | SP3 LGA4094 |
| Cooler in the box | None, server heatsink required |
Motherboard compatibility
AMD EPYC 7642 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7642 is
The EPYC 7642 is a 48-core, 96-thread server processor from Rome. It launched in August 2019 for cache heavy HPC with a 2.3 GHz base and up to 3.3 GHz boost at 225 W. Eight half populated chiplets deliver the full 256 MB of L3.
Two hundred fifty six megabytes of L3, the most of any 48-core Rome part, keep simulation meshes on package. Twenty four megabytes of L2 back parallel solvers. The 225 W envelope pays for cache and clocks together.
Dual socket scaling reaches 96 cores with half a gigabyte of L3 per box for large models. The 7642 costs more than the 7552 for cache sensitive codes. HPC partitions with big working sets fit here.
Socket and motherboard compatibility
The EPYC 7642 fits SP3 on single and dual socket boards rated for 225 W. Top tier power stages and cooling decide sustained clocks. Vendor qualification matters at this band.
HPC dual socket pairs total 96 cores with 512 MB of L3 for distributed solvers. High wattage redundant power follows the manual. The How to find your CPU socket type guide covers server sockets.
Milan cache heavy parts later continued the role on these boards with updates.
Memory, PCIe and cooling
Eight DDR4-3200 ECC channels feed 96 threads at up to 204.8 GB per sec. Large memory footprints pair with the huge cache for solver nodes. ECC guards long batch runs.
PCIe Gen4 lanes total 128 per socket for HDR networking and NVMe scratch. HPC fabrics attach directly to CPU lanes. Dual socket builds reach 160 lanes.
The 225 W class needs premium air or liquid cooling. Data center water temperatures decide boost more than air flow alone. Torque patterns follow the manual.
Where this Rome part fits
Forty eight cores with 256 MB of L3 fit CFD, weather and EDA partitions where cache decides runtime. Memory bandwidth per core matters less when meshes stay on package. Burst to 3.3 GHz helps serial sections.
Clusters standardize on dual socket 7642 pairs with HDR interconnects. Pair with balanced RAM per core for solvers. The AMD EPYC 7552 covers the same cores cheaper for throughput billing.
Benchmark the working set against cache size before paying the 7642 premium.
Upgrade paths
On SP3 density grows to 64-core 7742 parts on the same boards, or Milan X cache stacked SKUs for bigger working sets. Fabrics and storage carry over.
SP5 Genoa X parts serve later cache heavy refreshes. The CPU cooler compatibility by socket guide details 225 W cooling.
Frequently asked questions
What socket does the AMD EPYC 7642 use?
It uses SP3 on single and dual socket server boards.
How much cache does the 7642 have?
24 MB of L2 plus 256 MB of L3, the most of any 48-core Rome part.
What is the TDP of the EPYC 7642?
225 W with premium server cooling required.
Does the 7642 scale dual socket?
Yes. It runs one or two sockets.
When did the EPYC 7642 launch?
August 2019 with the Rome family.
Sources and verification
Facts last checked against these sources on . Page last edited on .