AMD EPYC 7371 socket: SP3

The AMD EPYC 7371 uses the SP3 socket on server boards. It is a 16 core Naples server chip for high clock single socket hosts.

Socket
SP3
Launched
November 2018
Cores and threads
16 and 32
Default TDP
200 W
Codename
Naples
Segment
Server
Family
AMD EPYC
Clocks
3.1 / 3.8 GHz

AMD EPYC 7371 specifications

Cores16
Threads32
Core architectureZen (Naples) cores on 14 nm
Clocks3.1 GHz base, up to 3.8 GHz
Cache64 MB L3, 8 MB L2
Processor base power (TDP)200 W
Manufacturing process14 nm
Memory supportDDR4 up to 2666 MT/s ECC, eight channels, up to 2 TB
PCI Express128 lanes from the CPU, PCIe 3.0
Integrated graphicsNone
MultiplierLocked
ECC memorySupported
PackageSocket SP3 (LGA, 4094 contacts)

Motherboard compatibility

AMD EPYC 7371 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.

SP3 at a glance

TypeLGA, 4,094 contacts
Package size58.5 × 75.4 mm
IntroducedJune 2017
MemoryDDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket
Cooler mounting holesBoard specific (server heatsink)

Read the full SP3 socket guide

What the EPYC 7371 is

The EPYC 7371 pushes Naples clocks with sixteen cores and multithreading. It launched in November 2018 with a 3.1 GHz base and up to 3.8 GHz boost at 200 W. AMD targets high frequency servers that need per core speed with server I/O.

Sixty four megabytes of L3 with 8 MB of L2 feed databases across 32 threads. The high base for a 16 core Naples part sustains transactions. Boost reaches 3.8 GHz for single thread peaks. Note that Technical City lists 170 W and TR4 socket for this SKU, while AMD specifications list 200 W and SP3, and this page uses the manufacturer values.

No integrated graphics is included. The process is 14 nm. DDR4 ECC in eight channels up to 2 TB suits large memories.

Socket and motherboard compatibility

The 7371 fits SP3 on server boards, not TR4 despite some list errors. Vendors wire 1P and 2P boards for Naples with 200 W power stages. Late 2018 BIOS builds carry 7371 IDs.

Eight channel DDR4 ECC RDIMMs up to 2666 MT per s carry large datasets. Balanced population sustains bandwidth near 170.6 GB per sec. The Socket vs chipset: what decides whether a CPU works guide covers server board lists.

Single socket use extracts the high clocks without inter socket latency. Dual socket operation remains supported where boards allow.

Memory, PCIe and cooling

DDR4 ECC in eight channels up to 2 TB covers high frequency databases. Matched DIMMs across channels feed 32 threads. Start with 256 GB for in memory work.

One hundred twenty eight Gen3 lanes from the CPU connect NVMe and 25 GbE at server rates. High clock hosts benefit most from low latency storage. Board splits follow vendor designs.

Two hundred watt server heatsinks with strong airflow are required. No retail cooler applies. Follow vendor torque and thermal interface guidance.

Upgrade paths

On the same socket, the AMD EPYC 7261 trims to eight cores at 170 W for efficient hosts. Larger 24 and 32 core Naples parts add threads where listed. Both share SP3 after a BIOS check.

Single socket Ryzen lacks the lanes and channels for such hosts. It suits labs rather than production.

Past SP3 Rome and Milan bring more cores per socket on many boards after updates. The 7371 covers high clock sixteen core servers where frequency matters.

Frequently asked questions

What socket does the EPYC 7371 use?

It uses SP3 on server boards, not TR4 as some lists show.

How many cores does the 7371 have?

Sixteen cores with multithreading give 32 threads. Base is 3.1 GHz with boost to 3.8 GHz.

What is the TDP of the 7371?

200 W per AMD specifications. Technical City lists 170 W, but this page uses the manufacturer value.

What memory does the 7371 support?

DDR4 ECC in eight channels up to 2 TB.

When did the 7371 launch?

November 2018.

Sources and verification

  1. AMD EPYC 7371 Drivers and Specifications (AMD)
  2. EPYC 7371 specs (Technical City)

Facts last checked against these sources on . Page last edited on .