AMD EPYC 7252 socket: SP3
The AMD EPYC 7252 uses SP3, the LGA socket for EPYC server processors. The 8-core chip at 120 W works in single and dual socket boards.
AMD EPYC 7252 specifications
| Cores | 8 |
|---|---|
| Threads | 16 |
| Core architecture | Zen 2 (Rome) |
| Clocks | 3.1 GHz base, up to 3.2 GHz boost |
| Cache | 4 MB L2 plus 64 MB L3 |
| Default TDP | 120 W |
| Manufacturing process | TSMC 7 nm FinFET |
| Memory support | DDR4 ECC RDIMM, 8 channels (AMD lists 4-channel DDR4-2667 as performance optimized) |
| PCI Express | 128 PCIe Gen4 lanes per socket, up to 160 in 2P |
| Integrated graphics | None (BMC graphics on board) |
| Multiplier | Locked |
| ECC memory | Supported, DDR4 ECC RDIMM |
| Package | SP3 LGA4094 |
| Cooler in the box | None, server heatsink required |
Motherboard compatibility
AMD EPYC 7252 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7252 is
The EPYC 7252 is an 8-core, 16-thread server processor from Rome. It launched in August 2019 for dual socket capable entry nodes with a 3.1 GHz base and up to 3.2 GHz boost at 120 W. Sixty four megabytes of L3 double the per core cache of the single socket 7232P.
High base clocks suit per core licensed software and latency sensitive gateways. Four megabytes of L2 back eight fast cores. The flat boost curve keeps behavior predictable across load swings.
Unlike P models, the 7252 scales to two sockets for 16-core clusters that grow by adding a second chip. Branch virtualization and storage nodes fit here. Dual socket readiness future proofs small racks.
Socket and motherboard compatibility
The EPYC 7252 fits SP3 on single and dual socket server boards. Board lists must name the SKU for the exact firmware. Rome posts natively on boards of its generation.
Dual socket boards allow starting with one 7252 and adding a second later. Memory and lane budgets double with the second socket. The How to find your CPU socket type guide maps server platforms.
Milan support later arrived on many boards through vendor BIOS, which extends 7252 systems to newer generations.
Memory, PCIe and cooling
DDR4 ECC spans 8 channels with 4-channel DDR4-2667 listed as performance optimized for this SKU. Matched RDIMMs hold speeds with ECC active. Population follows the manual per socket.
PCIe Gen4 gives 128 lanes per socket and up to 160 in dual socket builds. Entry clusters rarely saturate the lanes, which leaves growth for NICs. SATA hangs off spare lanes.
The 120 W band cools easily in 1U with standard heatsinks. No boxed cooler exists. Per core heat stays low on the multi chiplet package.
Where this Rome part fits
Eight fast cores fit firewalls, hyperconverged edge nodes and per core licensed databases. Clock speed beats core count for these roles. The 64 MB L3 keeps stateful services responsive.
Small clusters start single socket and scale to two sockets without board changes. Pair with modest RAM and 10 Gb networking. The AMD EPYC 7262 steps clocks higher nearby for license heavy roles.
Confirm board firmware carries Rome support before racking older Naples era boards.
Upgrade paths
On SP3 growth runs along core count to 12-core 7272 and 16-core 7282 parts, or by adding a second 7252. Milan SKUs follow with BIOS updates.
SP5 servers bring DDR5 for later refreshes. The CPU cooler compatibility by socket guide tracks server heatsink bands.
Frequently asked questions
What socket does the AMD EPYC 7252 use?
It uses SP3 on single and dual socket server boards.
How many cores does the EPYC 7252 have?
8 cores with 16 threads at 3.1 GHz base and up to 3.2 GHz boost.
Does the 7252 support dual socket?
Yes. Non-P Rome SKUs scale to two sockets.
What memory does the EPYC 7252 take?
DDR4 ECC RDIMM, with 4-channel DDR4-2667 as performance optimized.
What is the TDP of the EPYC 7252?
120 W with server cooling required.
When did the EPYC 7252 launch?
August 2019 with the Rome stack.
Sources and verification
Facts last checked against these sources on . Page last edited on .