AMD EPYC 9354 socket: SP5

What the EPYC 9354 is

AMD positions the EPYC 9354 as the 32-core member of the 4th Gen EPYC family for SP5 boards from November 2022. 32 Zen 4 cores with simultaneous multithreading give 32 cores and 64 threads, with base at 3.25 GHz and up to 3.8 GHz boost. The package carries 256 MB of L3. The 280 W envelope with a 240 to 300 W configurable window fits standard server heatsinks with front to back airflow.

DDR5 up to 4800 MT/s, ECC RDIMM, 12 channels, up to 6 TB per socket with ECC feed the cores, and matched DIMMs hold the rated speed. One hundred twenty eight Gen5 lanes per socket wire NICs, accelerators and NVMe. Boards run one or two sockets with the same memory and IO per CPU.

Dense virtualization and databases take this 32-core part with 256 MB of L3, where cache per core trims memory traffic at 280 W. Boards need an SP5 platform with the EPYC 9354 on the support list. The Socket vs chipset: what decides whether a CPU works guide covers server board choice, and AMD EPYC Embedded 9354 is the embedded counterpart on the same socket.

Socket and motherboard compatibility

The 9354 fits SP5 on single and dual socket server boards with LGA 6096 retention and server power delivery. Board lists must name the EPYC 9354 part for qualification.

Platform choice decides management and IO breadth rather than CPU fit. Boards carry BMC management, multiple NICs and NVMe backplanes for this power class. A BIOS that lists Genoa from November 2022 covers the part, while early firmware may need an update for specific stepping IDs. Check the board list before mixing this SKU with other steppings.

Memory, PCIe and cooling

DDR5 up to 4800 MT/s, ECC RDIMM, 12 channels, up to 6 TB per socket with ECC feed the cores, and matched RDIMMs hold the rated speed. Population with matched DIMMs holds the rated speed, and twelve channel operation needs one DIMM per channel at minimum for full bandwidth. Capacity reaches 6 TB per socket with high density DIMMs.

One hundred twenty eight Gen5 lanes per socket wire NICs, accelerators and NVMe. Lane bifurcation follows board firmware, so slot population rules come from the board manual.

The 280 W envelope needs a server heatsink with front to back airflow and a chassis with redundant fans. The large SP5 package uses a carrier with even mounting pressure. Paste and torque sequence follow the heatsink maker specification.

Upgrade paths

On SP5 the upward moves are higher core Genoa parts where VM counts grow, or adding a second EPYC 9354 socket where boards allow two socket operation. For this 32-core SKU, memory growth to full twelve channel population and NIC additions often help more than clocks.

Outside this SKU, AMD EPYC 9454P (EPYC 9454P) on SP5 trims or adds cores for lighter or denser loads. Bergamo parts trade per core cache for thread density, while Turin parts move the platform to 5th Gen on the same socket. A move to another socket needs a new board and memory plan, so socket local growth comes first.