AMD EPYC 8225P socket: SP6

What the AMD EPYC 8225P is

The AMD EPYC 8225P is the 24-core clock-tuned model of the EPYC 8005 Sorano family on Socket SP6. It runs 48 threads at 2.95 GHz base with boost to 4.5 GHz, backed by 128 MB of L3 cache and a 160 W default TDP. AMD announced Sorano in February 2026 and launched the stack in May 2026, building it on full Zen 5 cores with a 5nm process instead of the denser Zen 4c cores used in Siena.

Twenty-four cores at a 2.95 GHz base, the highest base clock in the Sorano stack, suit latency-sensitive edge roles such as radio access processing, firewalling and retail transaction hosts. Fewer cores at higher sustained clocks finish single flows sooner than denser models at lower bases. The 128 MB L3 pool keeps working sets resident for these leaner thread counts without paying for cache the workload never touches.

Against the 32-core 8325P above it, the 8225P trades 8 cores and half the L3 for a 0.25 GHz higher base and 15 W less draw. Against the 16-core 8125P below it, it adds 8 cores for busier sites while holding a similar clock-first character. No AMD 1Ku price is published on AMD pages for this model, so builders price it from board vendor quotes. The 8225P is the frequency pick of the Sorano middle.

Socket and motherboard compatibility

The 8225P fits Socket SP6, a 4,844-contact land grid array that AMD built for EPYC 8004 Siena processors from 8 to 64 cores and EPYC 8005 Sorano processors from 8 to 84 cores. Every board is single-socket only, so one 8225P fills the socket and there is no second-socket upgrade to plan. SP6 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Sorano is a drop-in replacement on Siena boards after a BIOS update from the board maker, at the same power class. The 8225P at 160 W sits well inside the Siena envelope, which keeps the swap simple on boards the vendor lists for Sorano. Memory on a converted board may stay at the Siena qualified speed rather than reaching DDR5-6400, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP6 socket feeds 6 DDR5 channels with ECC RDIMM modules, and AMD rates Sorano to 6400 MT/s for up to 3 TB per socket. Six channels at these rates keep 48 threads supplied in packet and transaction mixes with tight latency budgets. Population order, maximum capacity and per-board speed caps vary, so the vendor memory list governs every build. Latency-sensitive roles gain most from the fastest qualified DIMMs the board allows.

PCI Express connectivity is Gen 5 with x96 lanes per socket, plus x8 Gen 3 lanes that carry board devices and slower slots. That lane budget feeds NVMe storage, timing cards and 100-gigabit networking on a single-socket edge board without lane sharing pressure. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to an expansion layout. CXL 2.0 memory expansion is part of the Sorano platform where the board wires it.

Cooling follows the board vendor list rather than a retail box. SP6 uses server retention with heatsinks validated per TDP class, and the 8225P at 160 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a quiet or outdoor cabinet demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 8225P is the 32-core 8325P or the 48-core 8435P, staying on SP6 boards with attention to their higher TDP classes. The path down is the 16-core 8125P or the 8-core 8025P where smaller power envelopes or lower node cost matter more than thread count. Clock-first sites can step per node without touching rack layout. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP8 is a different platform with 8 memory channels, PCIe 6.0 and higher power classes, aimed at mainstream enterprise racks rather than compact edge nodes. That change replaces board, memory population and cooling design from scratch. Buyers coming from older tower or embedded servers face the same full-platform refresh. The decision turns on whether the workload fits a small single-socket edge node or needs mainstream rack density, and the answer differs for far-edge cabinets and for central clusters.