AMD Ryzen AI Embedded P174 socket: FP8

What the Ryzen AI Embedded P174 is

The Ryzen AI Embedded P174 is the 10-core member of the P100 high end, announced in March 2026 beside the 12-core P185 and 8-core P164. Four Zen 5 cores plus six Zen 5c cores give 20 threads with boost to 5.0 GHz, cache is 10 MB of L2 with 24 MB of L3, and graphics are 12 RDNA 3.5 compute units at up to 2800 MHz. The XDNA 2 NPU offers up to 50 TOPS. Default TDP is 28 W inside the 15 to 54 W configurable range on TSMC 4 nm.

The 10-core point exists for designs that want more than the 8-core model without paying for the top SKU: two extra CPU cores and the same 12 compute unit graphics as the P164, one step below the 16 units of the P185. Control software gets full Zen 5 cores with AVX-512 while vision loads share the GPU and NPU. The monolithic Gorgon Point die is the Strix Point refresh with higher clocks, faster power management and native LPDDR5X-8533.

Embedded terms match the series: continuous operation rating, 10-year supply with last time buy in 2036, and sampling from the March announcement toward third quarter production. Standard grade spans 0 to 105 degrees junction, and the AMD Ryzen AI Embedded P174i extends the low end to minus 40.

Socket and board compatibility

The P174 solders into FP8, the 25 × 40 mm BGA that spans Phoenix to Gorgon Point. The joint is permanent, so SKU, memory size and thermals are fixed per build. Production modules come from Advantech, congatec, Kontron and others, with chip-down layouts for volume.

Package commonality helps board reuse across generations, but firmware must know the APU, so older carriers need updates that name the P174. Documentation shipped with sampling.

Within the series the AMD Ryzen AI Embedded P185 adds two cores and four graphics units above, while the 8-core model saves budget below. The Halo class FP11 X100 series stands beyond FP11 for bigger designs.

Memory, PCIe and cooling

Boards use DDR5-5600 modules or soldered LPDDR5X up to 8533 MT/s, dual channel with ECC and Link-ECC options. The 12 compute unit GPU and 10 CPU cores share the pool, so bandwidth planning matters for vision plus control designs. Soldered capacity cannot grow later.

I/O gives 16 PCIe Gen4 lanes, two USB4 ports, USB 3.2 and 2.0, and four display outputs to 7680x4320. Lanes feed NVMe, networking and sensors per board manual, with optional B650 or X670 chipset expansion where designs need more. Integrated graphics cover display and compute without a discrete card.

Cooling is a system design for the configured TDP between 15 and 54 W on the lidless package. Validate sustained inference at continuous power rather than bursts, since edge nodes rarely idle. No boxed cooler exists.

Platform, software and lifecycle

AMD places the 10-core SKU in industrial automation, medical devices and pro AV that need solid multithreading with real graphics. Linux, Xen, FreeRTOS and ROCm cover control, separation, real-time tasks and GPU math, and the 10-year lifecycle to 2036 protects certifications.

The middle position is often the volume choice: enough cores for mixed workloads without the flagship price, and enough graphics for four 4K displays and inference beside them.

Upgrade paths

Soldered packages cannot be upgraded. A new build around a larger or smaller P100 SKU is the only move inside FP8, and Halo X100 parts need FP11 boards. Desktop Gorgon class silicon uses AM5.

Choose SKU and memory for the lifetime workload at the start, since neither changes in the field.