AMD EPYC 9996 socket: SP7

What the AMD EPYC 9996 is

The AMD EPYC 9996 is the flagship of the EPYC 9006 Venice stack and the highest core count part AMD sells on Socket SP7. It carries 256 Zen 6c cores with simultaneous multithreading for 512 threads, running at 2.55 GHz base with boost to 4.1 GHz. The package holds 1024 MB of L3 cache, which keeps 4 MB per core even at this density. AMD builds the compute dies on the TSMC 2 nm process and launched the family in July 2026.

Two hundred fifty-six cores at 600 W of default CPU power aim squarely at cloud hosts, dense virtualization clusters and consolidation projects where threads per rack decide cost. The large shared L3 pool steadies multi-tenant throughput when many virtual machines contend for the same data. Memory bandwidth matters as much as core count here, and the 16 DDR5 channels of the SP7 platform exist to feed exactly this kind of part. At 600 W the processor needs a board and chassis combination rated for the top power class, with liquid cooling on many vendor lists.

Against the 192-core 9966 below it, the 9996 adds 64 cores and 256 MB of cache for work that scales almost linearly with threads. The 1Ku price of 14904 USD works out to about 58 USD per core, the lowest per-core figure in the SP7 stack. Buyers who license software per core or who face strict power limits per rack may still prefer a smaller SKU. The 9996 is the choice when the goal is maximum threads per socket and the power and cooling budget allow it.

Socket and motherboard compatibility

The 9996 fits Socket SP7, a 7536-contact land grid array that AMD built for EPYC 9006 Venice processors from 64 to 256 cores. Boards come in single-socket and dual-socket layouts, and AMD validates this standard model for both, so one 9996 starts a system and a matched pair scales it to 512 cores. SP7 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P configuration needs two matched 9996 processors and a board wired for dual-socket operation, with memory populated to the vendor rules on both sockets. A 1P board takes one 9996 and suits a single dense node without the second-socket cost. Moving from an older SP5 Turin system is a full platform change with board, memory and heatsinks replaced together, since neither the socket nor the DIMM population carries over.

Memory, PCIe and cooling

Each SP7 socket feeds 16 DDR5 channels using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 1024 GB/s per socket with RDIMM and 1638.4 GB/s with MRDIMM. Sixteen channels at these rates keep 512 threads supplied in memory-bound analytics and virtualization mixes. Population order, maximum capacity and MRDIMM support vary by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 6 with x96 lanes per socket in the AMD specification, which carries NVMe arrays, high-rate networking and accelerators for AI host nodes. CXL 3.1 rides on the same fabric for memory expansion. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. The Gen 6 signaling shortens transfer times for nodes that stage accelerator data through system memory.

Cooling follows the board vendor list rather than a retail box. SP7 uses server retention with heatsinks validated per power class, and the 9996 at 600 W needs a kit rated for the top class in the intended chassis airflow, which often means liquid cooling. No cooler ships with the processor. Firmware power limits can cap draw below the default where a chassis or power budget demands it, at some cost in sustained clocks.

Upgrade paths

The 9996 sits at the top of the SP7 stack, so movement on the same socket goes down or sideways. The 192-core 9966 keeps the 600 W class with fewer cores for per-core licensed software, while the 168-core 9846 and 128-core 9756 drop to 500 W for tighter power envelopes. The frequency tuned 96-core 9686F and 64-core 9586F trade cores for boost to 5 GHz where single-thread speed matters. Each of these moves keeps board, memory and heatsink investments where the power class allows.

A move to SP8 is a different platform with 8 memory channels and more Gen 6 lanes per board, aimed at mainstream enterprise racks rather than maximum density per socket. That change replaces board, memory population and cooling design from scratch. Buyers coming from SP5 Turin systems face the same full-platform refresh. The decision turns on whether the workload needs SP7 threads per socket or SP8 balance per node.