AMD EPYC 9846 socket: SP7

What the AMD EPYC 9846 is

The AMD EPYC 9846 is the 168-core model of the EPYC 9006 Venice stack on Socket SP7. It runs 336 threads at 2.85 GHz base with boost to 3.7 GHz, backed by 768 MB of L3 cache and a 500 W default TDP. AMD launched the EPYC 9006 family in July 2026 on the TSMC 2 nm process, with SP7 as the high-bandwidth platform next to mainstream SP8. The 9846 sits between the 192-core 9966 and the 128-core 9756, pairing near-top cache capacity with a middle power class.

One hundred sixty-eight cores at 500 W suit large virtualization hosts, container platforms and scale-out databases that want high density without entering the 600 W cooling class. Sharing the 768 MB cache of the 9966 across fewer cores lifts per-core cache above 4.5 MB, which helps virtual machines and Java heaps that miss smaller pools. The 500 W envelope still demands a stout board and heatsink kit, but it opens chassis options that rule out the 600 W flagships. Operators often place this SKU where rack power is capped yet thread count still decides throughput.

Against the 9966 above it, the 9846 gives up 24 cores and 50 MHz of base clock while shedding 100 W and about 965 USD of 1Ku price, listed at 13114 USD. Against the 9756 below it, the 9846 adds 40 cores and 256 MB of cache at the same 500 W. Buyers who find the 600 W class impractical but the 128-core class thin land here. The 9846 is the bridge between flagship density and mid-stack efficiency.

Socket and motherboard compatibility

The 9846 fits Socket SP7, a 7536-contact land grid array that AMD built for EPYC 9006 Venice processors from 64 to 256 cores. Boards come in single-socket and dual-socket layouts, and AMD validates this standard model for both, so the same SKU serves a 1P storage-rich node and a 2P rack host. SP7 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P configuration needs two matched 9846 processors and a board wired for dual-socket operation, with both sockets populated to memory rules the vendor publishes. A 1P board takes one 9846 and suits single dense nodes in power-capped rows. Moving from an older SP5 Turin system is a full platform change with board, memory and heatsinks replaced together, since the socket changed and the DIMM population does not carry over.

Memory, PCIe and cooling

Each SP7 socket feeds 16 DDR5 channels using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the 9846 platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 1024 GB/s per socket with RDIMM and 1638.4 GB/s with MRDIMM. Sixteen channels at these rates keep 336 threads supplied in memory-bound analytics and virtualization mixes. Population order, maximum capacity and MRDIMM support vary by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 6 with x96 lanes per socket in the AMD specification, which carries NVMe arrays, high-rate networking and accelerators for data-heavy nodes. CXL 3.1 rides on the same fabric for memory expansion. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. The Gen 6 signaling shortens transfer times for replication and backup traffic that moves through system memory.

Cooling follows the board vendor list rather than a retail box. SP7 uses server retention with heatsinks validated per power class, and the 9846 at 500 W needs a kit rated for that class in the intended chassis airflow. High-performance air covers many 500 W installations, with liquid options where density or inlet temperatures demand it. No cooler ships with the processor. Firmware power limits can cap draw below the default where a chassis or power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9846 is the 192-core 9966 or the 256-core 9996 at 600 W, staying on SP7 boards with attention to the higher cooling class. The path down is the 128-core 9756 at the same 500 W, which suits per-core licensed software, or the 96-core 9656 at 400 W for efficiency-led fleets. The frequency tuned 96-core 9686F offers boost to 5 GHz for latency-sensitive roles at the cost of cores. Each of these moves keeps board, memory and heatsink investments where the power class allows.

A move to SP8 is a different platform with 8 memory channels and more Gen 6 lanes per board, aimed at mainstream enterprise racks rather than maximum density per socket. That change replaces board, memory population and cooling design from scratch. Buyers coming from SP5 Turin systems face the same full-platform refresh. The decision turns on whether the workload needs SP7 threads per socket or SP8 balance per node.