AMD EPYC 9116 socket: SP8

What the AMD EPYC 9116 is

The AMD EPYC 9116 is the 16-core standard model of the EPYC 9006 Venice stack on Socket SP8. It runs 32 threads at 2.85 GHz base with boost to 4.5 GHz, backed by 48 MB of L3 cache and a 160 W default TDP. AMD launched the EPYC 9006 family in July 2026 at its Advancing AI event, built on the TSMC 2 nm process, and positioned SP8 as the mainstream enterprise platform next to the larger SP7.

Sixteen cores at 160 W suit efficient virtualization nodes, content serving tiers and remote-office hosts where watts per virtual machine decide operating cost. The 2.85 GHz base holds steady under all-core loads, while the 4.5 GHz boost keeps interactive and control-plane tasks responsive. The 48 MB L3 pool is lean next to the cache-heavy F bins, which matches working sets that stream through memory rather than sitting in cache.

Against the 16-core 9176F, the 9116 gives up clocks and cache for a 40 W saving and a 1Ku price of 1200 USD against 3787 USD. Against the 8-core 9016 below it, the 9116 doubles cores and threads for denser consolidation at 30 W more. Buyers who need low cost per host favor this standard bin, while buyers who pay per core for database licenses look at the cache-heavy F bin.

Socket and motherboard compatibility

The 9116 fits SP8, a 5572-contact land grid array that AMD built for EPYC 9006 Venice processors from 8 to 128 cores. Boards come in single-socket and dual-socket layouts, and AMD validates this standard model for both, so the same SKU serves a 1P compact server and a 2P rack host. SP8 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P configuration needs two matched 9116 processors and a board wired for dual-socket operation, with both sockets populated to memory rules the vendor publishes. A 1P board takes one 9116 and suits power-constrained branches and small virtual clusters. Moving from an older SP6 or SP5 system is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the 9116 platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. For 32 threads this bandwidth keeps web tiers and file serving mixes supplied with headroom to spare. Population order, maximum capacity and MRDIMM support vary by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which carries NVMe arrays, high speed networking and accelerators without the lane sharing compromises of smaller platforms. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. The lane budget lets even an efficiency tuned host carry full I/O for backup and replication duties.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9116 at 160 W fits common air-cooled kits in 1U and 2U chassis. No cooler ships with the processor. Firmware power limits can cap draw below the default where a chassis or power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9116 is the 16-core 9176F for clocks and cache or the 24-core 9256 for more threads, both staying on SP8 boards with attention to their higher TDP classes. The path down is the 8-core 9016 where socket cost and power matter more than density. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP7 is a different platform with 16 memory channels and higher power classes, aimed at the largest cloud and HPC nodes rather than mainstream enterprise racks. That change replaces board, memory population and cooling design from scratch. Buyers coming from SP5 Turin systems face the same full-platform refresh. The decision turns on whether the site needs efficient SP8 nodes per branch or SP7 scale per socket, and the answer differs for distributed offices and for central compute halls.