SP7 socket: CPUs, chipsets and cooler fit
SP7 is AMD's high-end server socket for the EPYC 9006 Venice family. It is a land grid array socket with 7,536 contacts, and the package measures 123.6 × 100.6 mm. AMD launched the platform in July 2026 with Zen 6 and Zen 6c compute dies on TSMC 2 nm.
Quick facts
| Maker | AMD |
|---|---|
| Package type | LGA |
| Contacts | 7,536 |
| Package size | 123.6 × 100.6 mm |
| Introduced | July 2026 |
| Status | Current |
| Memory | DDR5, 16 channels per socket (RDIMM, 3DS RDIMM and MRDIMM up to 12800 MT/s) |
| PCIe from the CPU | PCIe 6.0 with 96 lanes plus 8 PCIe 4.0 lanes in 1P, and 128 lanes plus 16 PCIe 4.0 lanes in 2P. CXL 3.1. |
| Cooler mounting holes | Board specific (server heatsink) |
| Replaces | SP5 |
| Replaced by | None |
Overview
The socket feeds up to 256 cores and 512 threads per processor, with 16 channels of DDR5 memory and PCIe 6.0 links plus CXL 3.1. That combination targets dense virtualization hosts, databases and AI-adjacent serving nodes where memory bandwidth per core decides throughput.
SP7 replaces SP5 at the top of the stack while SP8 covers the mainstream range. Boards are vendor qualified per processor, so the board support list decides compatibility, power class and cooling, not the socket name alone.
Processor generations
| Codename | Marketing name | Years | Notes |
|---|---|---|---|
| Venice | EPYC 9006 series | 2026 | Zen 6 and Zen 6c server processors on TSMC 2 nm, from 64 cores to 256 cores, launched in July 2026. |
Memory layout
Each SP7 processor carries 16 channels of DDR5 across two onboard I/O dies. RDIMM and 3DS RDIMM cover capacity, while MRDIMM reaches 12800 MT/s in the platform table for bandwidth hungry nodes. Two DIMMs per channel is not the SP7 pattern, so population rules come from the board manual.
Bandwidth per core is the reason for 16 channels. A 256-core Venice part with 1024 MB of L3 still leans on memory for datasets that miss the cache, and MRDIMM exists for exactly that case. Check the vendor list for which speeds each board sustains at full population.
PCIe and CXL
Single-socket SP7 boards carry 96 PCIe 6.0 lanes plus 8 PCIe 4.0 lanes, and dual-socket boards carry 128 PCIe 6.0 lanes plus 16 PCIe 4.0 lanes. CXL 3.1 rides on the same fabric for memory expansion and accelerators. Lane counts vary by board wiring, so the block diagram of the exact board is the deciding document.
Compared with SP8, SP7 trades raw lane count for memory bandwidth. SP8 boards can expose more Gen 6 lanes, while SP7 keeps 16 memory channels. Match the socket to the bottleneck of the workload, not to the core count alone.
Power and cooling
SP7 parts span 200 W to 600 W of default CPU power, with the 256-core flagship at 600 W. Retention uses the SRM mechanism, and cooling ranges from high-performance air to liquid depending on the power class and chassis. The 600 W class needs a board and chassis combination rated for it.
Because power classes vary so widely, a board that runs a 200 W part may not be qualified for a 500 W or 600 W part. The vendor support list names allowed processors per board and per BIOS, including any power or airflow derating.
One socket or two
Most Venice SP7 models run in 1P or 2P configurations. Models with a P suffix, where they exist in the family, are single-socket only and priced below the dual-socket capable twin. F suffix models target high-frequency work with boost up to 5 GHz.
Upgrades stay inside the socket. Moving from SP5 Turin to SP7 Venice needs a new board, new DIMMs in the qualified speeds and a fresh cooling check, since neither the socket nor the memory population carries over.
CPUs on SP7
9 processor pages in the database, newest first.
| Processor | Cores / threads | Base / boost | TDP | Launched |
|---|---|---|---|---|
| AMD EPYC 9556 | 64 / 128 | 2.75 / 4.3 GHz | 300 W | Jul 2026 |
| AMD EPYC 9586F | 64 / 128 | 3.75 / 5.0 GHz | 500 W | Jul 2026 |
| AMD EPYC 9656 | 96 / 192 | 3.05 / 3.7 GHz | 400 W | Jul 2026 |
| AMD EPYC 9686F | 96 / 192 | 3.4 / 5.0 GHz | 500 W | Jul 2026 |
| AMD EPYC 9756 | 128 / 256 | 3.15 / 4.0 GHz | 500 W | Jul 2026 |
| AMD EPYC 9846 | 168 / 336 | 2.85 / 3.7 GHz | 500 W | Jul 2026 |
| AMD EPYC 9966 | 192 / 384 | 2.9 / 4.0 GHz | 600 W | Jul 2026 |
| AMD EPYC 9996 | 256 / 512 | 2.55 / 4.1 GHz | 600 W | Jul 2026 |
| AMD EPYC 9G76 | 96 / 192 | 3.4 / 4.8 GHz | 500 W | Jul 2026 |
Frequently asked questions
Which processors fit SP7?
EPYC 9006 Venice processors for Socket SP7, from 64 cores to 256 cores. EPYC Turin parts for SP5 do not fit, so check the board vendor list.
What is the difference between SP7 and SP8?
SP7 is the high-end platform with 16 memory channels and up to 600 W parts. SP8 is the mainstream platform with 8 memory channels, more PCIe 6.0 lanes per board and parts up to 400 W.
What memory does SP7 use?
DDR5 RDIMM, 3DS RDIMM and MRDIMM, up to DDR5-8000 and MRDIMM-12800 in the platform table. The board vendor qualifies exact DIMM types per board.
Does SP7 support one or two sockets?
Both, depending on the board. Single-socket boards take one SP7 processor, dual-socket boards take two. P-suffix EPYC models are single-socket only.
Sources and verification
- AMD EPYC 9006 Server CPUs for AI-First Data Centers (AMD)
- AMD Posts the Full EPYC 9006 SKU List: 31 Venice Parts (StorageReview)
- AMD Epyc 9006: Server-CPUs mit Zen 6 und 3D V-Cache (PC Games Hardware)
- AMD Server Processor Specifications (AMD)
Facts last checked against these sources on . Page last edited on .