AMD EPYC 9526 socket: SP8

What the AMD EPYC 9526 is

The AMD EPYC 9526 is the efficiency tuned 64-core model of the EPYC 9006 Venice stack on Socket SP8. It runs 128 threads at 2.75 GHz base with boost to 3.7 GHz, backed by 256 MB of L3 cache and a 220 W default TDP that AMD lets configure from 130 W to 220 W. AMD launched the EPYC 9006 family in July 2026 on the TSMC 2 nm process, with SP8 as the mainstream enterprise platform. The configurable power range makes this the flexible 64-core choice for fleets with mixed thermal limits.

Sixty-four cores at 220 W suit power-capped racks, colocation cages billed by the kilowatt and edge data rooms with limited cooling. Dropping the configurable TDP toward 130 W trims sustained clocks but keeps all 128 threads online, which favors throughput per watt over burst speed. The full 256 MB L3 cache stays available at every power setting, so cache-sensitive consolidation keeps its working sets regardless of the cap.

At a 1Ku price of 7123 USD the 9526 undercuts the faster 64-core 9536 while matching it in cores, threads and cache. Against the 9536 it gives up half a gigahertz of base clock and some boost headroom for 80 W less default draw. Against the 48-core 9456 it adds sixteen cores for denser hosts at a lower per-core power. Operators who meter energy closely start here and spend the savings on memory capacity.

Socket and motherboard compatibility

The 9526 fits Socket SP8, a 5572-contact land grid array covering EPYC 9006 Venice processors from 8 to 128 cores. AMD validates this standard model for single-socket and dual-socket boards, so the same SKU serves a 1P power-sipping node and a 2P efficiency host. Board vendors qualify memory lists, heatsink kits and firmware per TDP class, and the lower 220 W rating with its 130 W floor opens chassis options that hotter parts cannot use. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P build needs two matched 9526 processors with memory populated symmetrically across both sockets. A 1P build takes one processor, often in compact or airflow-limited chassis where the configurable TDP earns its keep. Since no P suffix twin exists, single-socket intent is expressed through the board rather than the SKU. Migration from SP5 Turin or SP6 Siena hardware is a full platform replacement of board, memory and cooling.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. Eight channels behind 64 cores is a comfortable ratio that keeps virtualization and analytics mixes fed even when the power cap trims clocks. Population order and capacity ceilings follow the board vendor list.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which carries NVMe arrays and fast networking with headroom on an efficiency node. Bifurcation tables and slot priorities live in board firmware, so I/O builds confirm the map before ordering. Gen 6 signaling moves twice the data per lane of Gen 5, which helps power-capped hosts finish transfers faster and return to idle sooner.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9526 at 220 W with its 130 W configurable floor fits a wider set of heatsink and chassis combinations than the 300 W class. No cooler ships with the processor. Facilities with strict inlet temperatures or acoustic limits find this the easiest 64-core SP8 part to house, provided the vendor qualifies the exact chassis and fan policy.

Upgrade paths

On the same socket, the path up from the 9526 is the 64-core 9536 where boost clocks matter more than watts, or the 96-core 9646 where thread count dominates, all staying on SP8 with the same memory and lane layout. The path down is the 48-core 9456 or the 32-core 9336 where lighter duties or license models favor fewer cores. Each step keeps board and memory investments where the TDP class allows, and moving up means rechecking heatsink ratings for the hotter class.

A move to SP7 is a different platform with 16 memory channels and higher power classes for flagship cloud and HPC nodes. That change replaces board, memory population and cooling from scratch and runs counter to efficiency goals unless density per socket is the priority. Buyers on SP5 Turin face the same full refresh. The 9526 is the answer when the constraint is watts per rack rather than cores per socket.