AMD EPYC 4584PX socket: AM5

What the EPYC 4584PX is

The EPYC 4584PX is a 16-core, 32-thread server processor that AMD released on May 21, 2024 as the stacked-cache flagship of the EPYC 4004 series. Zen 4 cores run at 4.2 GHz base with boost to 5.7 GHz. Cache is 128 MB of L3: 64 MB on-die across two compute dies with a 64 MB stacked 3D V-Cache slice. Default TDP is 120 W.

Maximum cache with maximum boost defines the top 4004 SKU for buyers who refuse to compromise: the same 128 MB stacking as the AMD EPYC 4484PX with four more cores and matching 5.7 GHz peak. Against the non-stacked AMD EPYC 4564P at 170 W it trades power and clocks for double the cache at the same price. AMD confirms the stacking in its 4004 blog and partner tables for channel planning. The boxed ordering part is 100-100001481WOF with tray 100-000001481 for flagship cached-hosting orders.

ECC memory through UDIMM and RDIMM keeps hosted tenants safe. The AMD page makes no multiplier claim, so this page records none. Launch pricing was set at 699 USD per 1Ku tray quantities for flagship cache buyers.

Workload fit is cache-first hosting at scale: game servers with large entity tables, trading databases and analytics stores where 128 MB of cache shortens every query. Operators pick the 4584PX where stacked cache lifts throughput more than extra cores would. The flagship cache buyer is usually a hosting provider standardizing one SKU across latency-sensitive tenants for uniform service levels and simpler support. The flagship cache buyer is usually a hosting provider standardizing one SKU across latency-sensitive tenants.

Socket and motherboard compatibility

The 4584PX fits the AM5 socket in LGA-1718 packaging on single-socket server boards. EPYC 4004 SKUs run on 1P designs only, and stacked-cache SKUs need firmware new enough to initialize the extra die on first boot. The board maker CPU support list confirms the minimum BIOS for this exact SKU.

Server boards differ from desktop AM5 models in ECC routing and BMC management for 24-hour duty. Production hosting belongs on purpose-built EPYC 4004 boards rather than repurposed desktop designs, even though the socket matches.

The 12-core stacked AMD EPYC 4484PX below shares the platform for lighter cached hosting at matching power with simpler thermals. Sockets, memory and PCIe generations match across both for common spares.

Memory, PCIe and cooling

DDR5-5200 ECC in 2 channels to 192 GB is the rated fit through UDIMM and RDIMM. Stacked cache reduces memory pressure, but fully populated channels still matter for bandwidth uniformity across 16 cores under full subscription load. The AMD blog confirms ECC-enabled DDR5-5200 as the family standard.

PCIe 5.0 x28 lanes from the CPU serve boot NVMe, networking and an optional card on entry boards. Few small boards wire every lane, yet controllers never wait on this CPU for hosting throughput. Board manuals define the fitted slots per chassis.

Cooling at 120 W uses server-rated tower or rack heatsinks matched to chassis airflow. Tray and WOF editions ship without a cooler for the 120 W stacked flagship class. Stacked cache prefers low temperatures for sustained boost, so a mid-range tower beats a minimal sink. The AM5 fixed-backplate pattern from the CPU cooler compatibility by socket guide applies.

Upgrade paths

Inside AM5 the 4584PX is the top of the 4004 stack for cached hosting with room for tenant growth: owners of the AMD EPYC 4484PX gain four cores with matching cache while keeping board and memory for years. The non-stacked AMD EPYC 4564P beside it trades cache for clocks at higher power for speed-bound hosting at any scale.

Moving to the Zen 5 based EPYC 4005 series brings newer cores on the same socket for refresh cycles. Leaving AM5 entirely means new boards with fresh memory for larger SP5-class platforms.