AMD EPYC 4484PX socket: AM5

What the EPYC 4484PX is

The EPYC 4484PX is a 12-core, 24-thread server processor that AMD released on May 21, 2024 with stacked cache for the EPYC 4004 series. Zen 4 cores run at 4.4 GHz base with boost to 5.6 GHz. Cache is 128 MB of L3: 64 MB on-die across two compute dies with a 64 MB stacked 3D V-Cache slice. Default TDP is 120 W.

Stacked cache is the reason this SKU exists for latency-sensitive hosting businesses: the extra die doubles cache against the 64 MB AMD EPYC 4464P for game servers, trading databases and latency-sensitive hosting that reuse large working sets around the clock. AMD confirms the stacking in its 4004 blog and partner tables, and the database breaks it out as two 32 MB 2D segments with one 64 MB 3D slice. The boxed ordering part is 100-100001482WOF with tray 100-000001482 for volume cached-hosting deployments.

ECC memory through UDIMM and RDIMM keeps hosted tenants safe from single-bit faults. The AMD page makes no multiplier claim, so this page records none. Launch pricing was set at 599 USD per 1Ku tray quantities for cache-first hosting buyers.

Workload fit is cache-first hosting: game servers with large entity tables, in-memory analytics and financial tick stores where hit rates decide throughput. Operators pick the 4484PX where 128 MB of cache shortens queries more than extra cores would for their tenant mix. Trading-adjacent hosts value the combination of 5.6 GHz boost with deep cache for order-book work that never leaves silicon or sleeps through market hours.

Socket and motherboard compatibility

The 4484PX fits the AM5 socket in LGA-1718 packaging on single-socket server boards. EPYC 4004 SKUs run on 1P designs only with firmware carrying the SKU ID. The board maker CPU support list confirms the minimum BIOS, and stacked-cache SKUs need firmware new enough to initialize the extra die on first boot and after updates.

Server boards differ from desktop AM5 models in ECC routing and BMC management for 24-hour duty. Production hosting belongs on purpose-built EPYC 4004 boards rather than repurposed desktop designs, even though the socket matches.

The 12-core AMD EPYC 4464P below shares the platform for uncached workloads at lower power with simpler cooling and smaller budgets. Sockets, memory and PCIe generations match across both for common spares in cached-hosting fleets.

Memory, PCIe and cooling

DDR5-5200 ECC in 2 channels to 192 GB is the rated fit through UDIMM and RDIMM. Large stacked cache reduces memory pressure, but fully populated channels still matter for bandwidth uniformity across 12 cores under full load and peak traffic. The AMD blog confirms ECC-enabled DDR5-5200 as the family standard for reliable cached hosting.

PCIe 5.0 x28 lanes from the CPU serve boot NVMe, networking and an optional card on entry boards. Few small boards wire every lane, yet controllers never wait on this CPU for hosting throughput. Board manuals define the fitted slots per chassis.

Cooling at 120 W uses server-rated tower or rack heatsinks matched to chassis airflow. Tray and WOF editions ship without a cooler. Stacked cache prefers low temperatures, so a mid-range tower beats a minimal sink for sustained boost through long sessions. The AM5 fixed-backplate pattern from the CPU cooler compatibility by socket guide applies.

Upgrade paths

Inside AM5 the 4484PX is a destination for cache-sensitive hosting rather than a stepping stone for general growth: owners of the AMD EPYC 4464P gain stacked cache for latency-bound work while keeping board and memory intact. The 16-core stacked AMD EPYC 4584PX above adds threads for denser cached hosting with matching cache depth and power headroom.

Moving to the Zen 5 based EPYC 4005 series brings newer cores on the same socket for refresh cycles. Leaving AM5 entirely means new boards with fresh memory for larger SP5-class platforms.