Intel Xeon Phi 7235 socket: LGA 3647

What the Xeon Phi 7235 is

The Xeon Phi 7235 is a sixty four core, two hundred fifty six thread many core accelerator from Knights Mill. It launched in December 2017 with a 1.3 GHz base and up to 1.4 GHz Turbo at 250 W. Sixty four cores with four threads each cover HPC nodes where throughput beats single thread pace.

Thirty two megabytes of shared L2 cache feed sixty four cores over 2D mesh. The low 1.3 GHz base keeps power in check across many cores, while 1.4 GHz burst lifts lightly threaded setup tasks. Two hundred fifty watts need server airflow with high static pressure.

Sixteen gigabytes of on package MCDRAM at 400+ GB/s feed bandwidth hungry kernels. Six channel DDR4-2133 up to 384 GB per socket holds larger datasets with ECC. Nodes boot from DDR4 while hot loops stay in MCDRAM.

Intel aimed Knights Mill at machine learning training with lower precision math over Knights Landing double precision. Single precision throughput doubles against prior Phi, with new vector neural instructions for integer work. Locked multiplier keeps cluster behavior uniform.

Socket and motherboard compatibility

The 7235 fits LGA 3647 on HPC server boards with Knights Mill firmware. Boards need a BIOS that lists Phi x200 parts and MCDRAM modes. It runs single socket per node designs, not dual socket pairs.

Server boards wire six DDR4 channels plus MCDRAM modes (cache, flat, hybrid) per Intel guidance. PCIe x16 links the Phi to hosts where used as a coprocessor, though socketed 7235 runs as a host CPU itself. The Socket vs chipset: what decides whether a CPU works guide covers server matching.

The Xeon Phi 7285 on the same socket adds four cores. Standard Xeon Scalable parts on LGA 3647 suit general servers where single thread matters more.

Memory, PCIe and cooling

DDR4-2133 ECC in six channels up to 384 GB per socket plus 16 GB MCDRAM is the memory design. MCDRAM modes follow workload guidance for cache or flat use. Bandwidth peaks near 102 GB per sec on DDR4 plus 400+ GB/s on MCDRAM.

Sixteen PCIe 3.0 lanes from the Phi wire networking and NVMe in single socket nodes. HPC fabrics take primary slots. Board manuals detail lane splits.

Two hundred fifty watts cool with server heatsinks and front to back airflow. Inlet temperature decides sustained all core pace.

Upgrade paths

On LGA 3647 the move is Phi 7295 for more cores and clocks, reusing board and DDR4 where firmware allows it. Most clusters add nodes before new Phis.

Past Knights Mill Intel ended Phi lines, so growth means Xeon Scalable or accelerators on new platforms. MCDRAM tuning helps more than clock chasing on Phi.