Intel Xeon 2.4 socket: Socket 604
The Intel Xeon 2.4 uses the Socket 604 socket. It is a Prestonia server part at 2.40 GHz with Hyper-Threading and 512 KB of L2 cache for dual-processor Socket 604 servers with DDR memory.
- Socket
- Socket 604
- Launched
- November 2002
- Cores and threads
- 1 and 2
- Base power
- n/a
- Codename
- Prestonia
- Segment
- Server
- Family
- Intel Xeon
- Clocks
- 2.39 GHz
Intel Xeon 2.4 specifications
| Cores | 1 |
|---|---|
| Threads | 2 |
| Core architecture | Prestonia cores on 130 nm |
| Clocks | 2.40 GHz (no turbo) |
| Cache | 512 KB L2 |
| Manufacturing process | 130 nm |
| Memory support | DDR through the server chipset |
| Front side bus | 533 MT/s |
| PCI Express | PCI-X from the board chipset |
| Integrated graphics | None |
| Multiplier | Locked (18x) |
| ECC memory | Yes, registered ECC |
| Package | Socket 604 (604-pin mPGA) |
Motherboard compatibility
Intel Xeon 2.4 needs a motherboard with a Socket 604 socket. Chipset by chipset data for this codename is not recorded yet. See the Socket 604 chipset list and the board maker's CPU support list.
Socket 604 at a glance
| Type | PGA, 604 contacts |
|---|---|
| Package size | n/a |
| Introduced | 2002 |
| Memory | DDR2 memory through the Caneland board chipset |
| Cooler mounting holes | Board specific (server heatsink) |
What the Xeon 2.4 is
The Intel Xeon 2.4 is a 2.40 GHz single-core server processor with Hyper-Threading from November 2002. It runs one NetBurst Prestonia core at 2.40 GHz with no turbo, so 1 core gives 2 threads. Cache is 512 KB of L2 on a 130 nm process. The package is Socket 604 for dual-processor servers with DDR memory. This page omits a TDP rating because the Prestonia table entry for the 2.4B gives no power figure in opened sources, while the cpu_list 89 W and 2.394 GHz values lack direct table support at these exact precisions. The cpu_list 2.394 GHz precision is kept in the quick field with the table 2.40 GHz used in prose.
Prestonia B suffix models use Socket 604 with a 533 MT/s front side bus and an 18x multiplier, which separates the 2.4B covered here from 2.4 GHz Socket 603 A parts on a 400 MT/s bus. Intel placed the 2.4B in November 2002. The chip supports MMX, SSE, SSE2 and Hyper-Threading.
Dual-processor scope with Hyper-Threading suited departmental servers. Two 2.4B parts give four threads per chassis, which helped threaded tasks before dual-core designs. That is why Prestonia B parts remained common after Gallatin added cache at higher prices.
Socket and motherboard compatibility
The Xeon 2.4 Prestonia fits Socket 604 dual-processor server boards with DDR memory and Prestonia B support. It needs a two-socket board with 533 MT/s paths. The Socket vs chipset: what decides whether a CPU works guide covers pairing rules.
Two-socket rack servers are the natural match. Boards listing Prestonia B parts accept the chip with server cooling. Socket 603 A parts need 400 MT/s boards instead.
Memory, PCIe and cooling
Memory is DDR through the server chipset with registered ECC modules. The CPU has no memory controller.
A 533 MT/s front side bus ties the CPUs to the chipset, while PCI-X slots hang off the chipset. No PCIe lanes originate on the die. Cooling uses vendor qualified server heatsinks per socket with chassis airflow.
Upgrade paths
On Socket 604 Prestonia steps include higher B clocks where listed. Gallatin DP parts offer L3 cache alternatives. Nocona parts offer 90 nm successors. Beyond Socket 604 a move to LGA 771 needs new boards. The 2.4 lifts with the lever, so swaps need no solder work.
Frequently asked questions
What socket does the Xeon 2.4 use?
Socket 604, in dual-processor servers with Prestonia B support.
How many cores does the Xeon 2.4 have?
One core and 2 threads at 2.40 GHz with 512 KB of L2 cache.
What memory works with the Xeon 2.4?
DDR through the server chipset with registered ECC modules.
Can the Xeon 2.4 be upgraded?
Higher Prestonia B clocks share the socket. Gallatin parts add L3 cache where listed.
Sources and verification
Facts last checked against these sources on . Page last edited on .