AMD EPYC 7601 socket: SP3

What the EPYC 7601 is

The EPYC 7601 is a thirty two core, sixty four thread server processor and the Naples flagship. It launched on June 20, 2017 with a 2.2 GHz base and up to 3.2 GHz boost at 180 W. The highest base in the 32 core Naples set gives it the lead in both single thread bursts and sustained all core work.

Sixty four megabytes of L3 cache across four dies feed large virtual fleets. Boost to 3.2 GHz covers up to twelve active cores, while heavier core counts settle to 2.7 GHz per core activity tables. The 14 nm multi chip module carries 19.2 billion transistors for the package.

No integrated graphics are present, so consoles run through board BMC graphics. ECC DDR4 in eight channels up to 2 TB per socket is the memory design for uptime. The multiplier is locked.

AMD priced the 7601 at $4,200 at launch as the top Naples SKU. Clouds that needed maximum Naples pace without moving to later generations chose it for dense hosts. It runs in one or two socket configurations.

Socket and motherboard compatibility

The 7601 fits SP3 on single and dual socket boards with Naples firmware. Vendor support lists name board revisions that carry 180 W flagships. Dual socket builds reach 64 cores per node with full I/O per CPU.

Boards expose eight DDR4 channels and 128 PCIe lanes per socket for flagship nodes. Power delivery and airflow for 180 W sustained loads decide board choice more than chipset names, since Naples integrates I/O on package. The Socket vs chipset: what decides whether a CPU works guide covers server matching.

The 32 core AMD EPYC 7551 is the lower clock sibling on the same boards. The 24 core AMD EPYC 7451 trims cores where licenses charge per core.

Memory, PCIe and cooling

DDR4-2666 ECC across eight channels up to 2 TB per socket gives up to 170.7 GB per sec of raw bandwidth. One DIMM per channel is the pace path to 2666, with 2400 common at two DIMMs per channel. RDIMM, LRDIMM and 3DS variants appear in board lists.

PCIe 3.0 with 128 lanes per CPU serves 100 GbE NICs, HBAs and NVMe shelves. Flagship nodes split lanes between network and storage for balanced throughput. Retimer needs follow board trace length guidance.

Cooling uses the SP3 slide carrier with three screws and vendor 180 W heatsinks. High flow 2U chassis suit flagship parts. Thermal paste covers the large multi die spreader per manual patterns.

Upgrade paths

On SP3 there is no higher Naples above the 7601, so growth means Rome or Milan on the same socket where boards and firmware allow it. Many 2019 SP3 boards accept Milan after a maker BIOS update, which keeps DDR4 platforms useful.

Past SP3 the path is SP5 with DDR5 and Gen5 lanes. Flagship owners often add memory and network before new CPUs. Used 7601 servers suit labs that want top Naples pace at low entry cost.