SP1 socket: CPUs, chipsets and cooler fit

SP1 is AMD ball grid array package with 1021 contacts in a 27 × 27 mm lidless footprint. It solders directly to server boards and carries ARM Cortex-A57 cores with memory controllers, PCIe, SATA and Ethernet in one chip. AMD lists the series as Opteron A1100 SoC, formerly called Seattle.

Quick facts

MakerAMD
Package typeBGA
Contacts1,021
Package size27 × 27 mm
IntroducedJanuary 2016
StatusLegacy
MemoryDDR3L and DDR4 with ECC, two channels, up to 1866 MT/s
PCIe from the CPUPCIe 3.0 with 8 lanes from the SoC, plus SATA and 10 Gb Ethernet
Cooler mounting holesNot applicable (soldered)
ReplacesNone
Replaced byNone

Overview

The package launched in January 2016 with three SKUs for storage, web and networking racks. A1120 brings four cores at 1.7 GHz and 25 W, A1150 brings eight cores at 1.7 GHz and 32 W, and A1170 brings eight cores at 2.0 GHz and 32 W. All share up to 4 MB of shared L2 and 8 MB of shared L3, with TrustZone and crypto units on die.

Memory covers DDR3L and DDR4 with ECC in two channels for dense nodes. PCIe runs at version 3.0 with 8 lanes for HBAs and NICs, while the SoC adds 14 SATA 6 Gb/s ports and dual 10 Gb Ethernet. Because the chip is soldered, core count and I/O are fixed at board purchase.

Processor generations

CodenameMarketing nameYearsNotes
SeattleOpteron A1100 Seattle2016ARM Cortex-A57 server SoCs including A1120, A1150 and A1170, launched in January 2016 on Socket SP1 with DDR4 and 10 Gb Ethernet.

Who Socket SP1 serves

Socket SP1 belongs in cold storage shelves, web front ends and networking appliances where watts per node matter. Eight core A1150 and A1170 nodes pack threads for object stores with many spindles. Quad core A1120 nodes suit gateways and control planes with lighter thread needs.

Boards mount the lidless die under a vendor heatsink with controlled pressure, so service follows the board manual rather than desktop practice. Nodes boot standard UEFI and Linux builds for ARMv8, with KVM and Xen support for virtual guests. Power capping trims clocks where racks run hot.

Memory and PCIe

Memory support covers registered DIMM and SODIMM options with ECC for data safety. DDR4 at 1866 MT/s lifts file throughput over DDR3L at 1600 MT/s. Up to 128 GB fits on developer boards with four slots, while production nodes size memory to cache and table needs.

PCIe arrives as version 3.0 with 8 lanes from the SoC, wired as x8, x4 pairs or x2 groups for HBAs and network cards. SATA dominates bulk storage with 14 ports at 6 Gb/s on reference designs. Dual 10 Gb Ethernet cuts a NIC slot in many builds.

Identification is simple in maker documents: socket reads SP1 and package reads BGA-1021 at 27 mm x 27 mm. That line separates SP1 from FT3 embedded parts at 769 contacts and from SP6 server parts at a larger LGA count. The LGA, PGA and BGA: CPU package types explained guide explains why soldered server packages stay with their boards.

CPUs on SP1

3 processor pages in the database, newest first.

ProcessorCores / threadsBase / boostTDPLaunched
AMD Opteron A11204 / 41.7 GHz25 WJan 2016
AMD Opteron A11508 / 81.7 GHz32 WJan 2016
AMD Opteron A11708 / 82.0 GHz32 WJan 2016

Frequently asked questions

Can a Socket SP1 processor be replaced or upgraded?

No. The SoC solders to the board in a lidless BGA-1021 package. Upgrading means replacing the board or the whole node.

What is the difference between Socket SP1 and Socket FT3?

Socket SP1 at 1021 contacts serves ARM Cortex-A57 Seattle SoCs with DDR4 and 10 Gb Ethernet for servers. Socket FT3 at 769 contacts serves x86 Jaguar and Puma APUs with DDR3 for embedded. The two do not interchange.

What memory does Socket SP1 use?

Boards use DDR3L or DDR4 with ECC in two channels, up to 1866 MT/s on DDR4. A1170 supports DDR3 at 1600 MT/s or DDR4 at 1866 MT/s per maker data.

What PCIe and I/O does Socket SP1 provide?

PCIe 3.0 with 8 lanes from the SoC for storage and network controllers, plus 14 SATA 6 Gb/s ports and dual 10 Gb Ethernet on board designs.

Sources and verification

  1. AMD Opteron A1100 SoC launch (AMD)
  2. Seattle cores on WikiChip

Facts last checked against these sources on . Page last edited on .