Cyrix MII-300GP socket: Super Socket 7

The Cyrix MII-300GP uses the Super Socket 7 socket. It is a single-core MII desktop part at 233 MHz with 64 KB of unified L1 cache for Super Socket 7 value boards.

Launched
April 1, 1998
Cores and threads
1 and 1
Base power
n/a
Codename
MII
Segment
Desktop
Family
Cyrix MII
Clocks
0.23 GHz

Cyrix MII-300GP specifications

Cores1
Threads1
Core architectureMII (M2)
Clocks233 MHz base, no turbo
Cache64 KB unified L1, L2 on board modules
Manufacturing process0.25 micron
Memory supportEDO DRAM and SDRAM through the board chipset
Front side bus66 MHz
PackageSuper Socket 7 (CPGA, 321 contacts)
MultiplierLocked (3.5x)
Integrated graphicsNone

Motherboard compatibility

Cyrix MII-300GP needs a motherboard with a Super Socket 7 socket. Chipset by chipset data for this codename is not recorded yet. See the Super Socket 7 chipset list and the board maker's CPU support list.

Super Socket 7 at a glance

TypePGA, 321 contacts
Package sizen/a
IntroducedMay 1998
MemoryEDO DRAM and SDRAM through the board chipset
Cooler mounting holesSocket lug (clip)

Read the full Super Socket 7 socket guide

What the MII-300GP is

The Cyrix MII-300GP is a 233 MHz single-core desktop processor from April 1998. It runs one M2 core at 233 MHz with no turbo, so 1 core gives 1 thread. Cache is 64 KB of unified L1 with no on-die L2 on a 0.25 micron process with 6.5 million transistors. Power is a modest envelope in a Super Socket 7 CPGA package on a 66 MHz front side bus with a 3.5x multiplier at 2.9 V.

The PR300 performance rating compares the chip against faster-clocked rivals, which is why the 300GP name maps to 233 MHz silicon. Later DZ steppings run 225 MHz on a 75 MHz bus. Cyrix launched MII parts in April 1998 with IBM and National Semiconductor production, later TSMC. The chip supports MMX.

A PR300 rating with a tiny transistor count suits Super Socket 7 value towers with EDO memory. The 66 MHz bus keeps board timing relaxed. That is why the MII-300GP shipped in budget home boxes.

Socket and motherboard compatibility

The MII-300GP fits Super Socket 7 value desktops with Cyrix support. It needs a 321-pin board with a 66 MHz bus and a BIOS that lists Cyrix MII parts. The Socket vs chipset: what decides whether a CPU works guide covers pairing rules.

Value EDO towers are the natural match. Boards listing MII-300GP accept the chip with a small clip cooler. Boards with AMD-only microcode tables may refuse the Cyrix CPUID string.

Memory, PCIe and cooling

Memory is EDO DRAM and SDRAM through the board chipset, matched to the board sockets. The CPU has no memory controller and no on-die L2, so board cache modules carry the second level. Value boards commonly run EDO pairs.

A 66 MHz front side bus ties the CPU to the chipset, while PCI hangs off the chipset. No AGP lanes come from this era on all boards and no PCIe lanes exist. Cooling uses the socket lug clip with a small cooler.

Upgrade paths

On the same socket, an AMD K6-2 with MMX and 3DNow keeps the board for higher clocks when the support list names it. A WinChip 2-250 such as IDT WinChip 2-250 is the Centaur rival at matching ratings with lower power.

A move to Slot A Athlon needs a new board. The Super Socket 7 page lists the MII to Sharptooth range for planning. Note: no two-source TDP was found for this string, so the power row is omitted.

Frequently asked questions

What socket does the MII-300GP use?

Super Socket 7. It is an MII desktop part at 233 MHz with a PR300 rating.

Why is a 233 MHz chip called 300GP?

The PR300 name is a performance rating against faster rivals. The silicon runs at 233 MHz on a 66 MHz bus.

What memory does the MII-300GP use?

EDO DRAM and SDRAM through the board chipset, with L2 cache on board modules.

What is the upgrade path from the MII-300GP?

An AMD K6-2 on the same support list, or a WinChip 2-250 rival part.

Sources and verification

  1. Cyrix MII model data M2 core (ZXC Wiki)
  2. Cyrix MII-300GP 225MHz sample (Tims collection)
  3. Super Socket 7 Cyrix MII (Wikipedia)

Facts last checked against these sources on . Page last edited on .