Intel Xeon MP 7030 Dual-Core socket: Socket 604

What the Xeon MP 7030 Dual-Core is

The Intel Xeon MP 7030 Dual-Core is a two-core multiprocessor server processor from December 2005. Each NetBurst core runs at 2.8 GHz through a 14x multiplier on an 800 MT/s front side bus. Hyper-Threading is documented for every Paxville MP model, so the two cores present 4 threads to the operating system. The sSpec is SL8UB on stepping A0, and the process is 90 nm in a 604-pin package for Socket 604.

Cache is 1 MB of L2 per core, written as 2x1 MB across the package, with no L3 on the die. Wikipedia records exactly this layout with the 800 MT/s bus and the 14x multiplier for SL8UB, and Intel's November 2005 launch release describes the 7030 as 2.80 GHz with 2x1 MB of L2 on an 800 MHz bus. That release announced the 7000 sequence as shipping on November 1, 2005 into existing E8500 chipset platforms, while TechPowerUp dates this per-SKU entry to December 2005. This page uses December 2005 from the per-SKU database and notes the November sequence announcement.

Power is a clean 135 W from TechPowerUp, matching the envelope of the other 70xx dual-core parts. The multiplier is locked, so frequency plans rest on the 14x ratio and the 800 MT/s bus. ECC memory is supported through the board, which matters for the multiprocessor database and consolidation roles this chip was sold into.

Socket and motherboard compatibility

The processor fits Socket 604, the 604-pin mPGA604 zero insertion force socket. As an MP part it targets boards that scale to four sockets and beyond, the quad and octo topology Wikipedia assigns to Paxville MP. Dual-socket DP boards are a separate qualification population even where they share the socket.

Intel stated at launch that the 7000 sequence fits existing platforms built around the E8500 chipset, which had been designed for dual-core operation. Even so, the board CPU list must name the 7030 or sSpec SL8UB explicitly, and the BIOS must carry its microcode. Power regulation must be rated for a 135 W part. The Socket vs chipset: what decides whether a CPU works guide explains how socket, chipset generation, and BIOS revision combine on server boards.

For a used system, confirm the board list entry, the BIOS revision, and the chassis airflow for a fully populated 135 W multiprocessor layout. Memory and slot behavior follow the board and chipset, so the board manual governs those details.

Memory, PCIe and cooling

Memory reaches the cores through the server board, and TechPowerUp records ECC support with a dual-channel board memory bus for this SKU. The memory type, speed grades, rank rules, and capacity ceiling are board facts from the server maker memory list. Population order matters on multiprocessor boards, so slots should be filled exactly as the manual prescribes rather than by guesswork.

Expansion hangs off the board chipset behind an 800 MT/s front side bus. There is no integrated graphics and no on-die PCIe controller, so slot versions, lane counts, and console behavior come from the board documentation. Remote management hardware or basic board graphics handles console output on these headless designs.

Cooling uses vendor heatsinks at the 135 W level. The correct part is the server maker heatsink specified for the exact board and chassis, installed in the directed airflow path the manual describes. A 135 W multiprocessor population leaves no margin for undersized or mismatched thermal parts.

Upgrade paths

Same-socket steps up are the 3.0 GHz Paxville MP parts: the Intel Xeon MP 7040 Dual-Core on a 667 MT/s bus and the Intel Xeon MP 7041 Dual-Core on an 800 MT/s bus, both with 2 MB of L2 per core. Each needs a board list entry and a BIOS that covers its sSpec. The 65 nm Tulsa generation is the later same-socket family, for example the Intel Xeon 7140M, where the board vendor qualifies it.

A move beyond Socket 604 to any newer Xeon generation requires a new board, new memory, and a new thermal plan, since sockets and chipsets both change.